
library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

package CONV_PACK_AZALIA_BLOCK is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_AZALIA_BLOCK;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity FRAME_SYNC_DW01_inc_0 is

   port( A : in std_logic_vector (6 downto 0);  SUM : out std_logic_vector (6 
         downto 0));

end FRAME_SYNC_DW01_inc_0;

architecture SYN_rpl of FRAME_SYNC_DW01_inc_0 is

   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component HAX1
      port( A, B : in std_logic;  YC, YS : out std_logic);
   end component;
   
   signal carry_6_port, carry_5_port, carry_4_port, carry_3_port, carry_2_port 
      : std_logic;

begin
   
   U1_1_5 : HAX1 port map( A => A(5), B => carry_5_port, YC => carry_6_port, YS
                           => SUM(5));
   U1_1_4 : HAX1 port map( A => A(4), B => carry_4_port, YC => carry_5_port, YS
                           => SUM(4));
   U1_1_3 : HAX1 port map( A => A(3), B => carry_3_port, YC => carry_4_port, YS
                           => SUM(3));
   U1_1_2 : HAX1 port map( A => A(2), B => carry_2_port, YC => carry_3_port, YS
                           => SUM(2));
   U1_1_1 : HAX1 port map( A => A(1), B => A(0), YC => carry_2_port, YS => 
                           SUM(1));
   U1 : INVX2 port map( A => A(0), Y => SUM(0));
   U2 : XOR2X1 port map( A => carry_6_port, B => A(6), Y => SUM(6));

end SYN_rpl;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity InBlock_1_DW01_inc_1 is

   port( A : in std_logic_vector (7 downto 0);  SUM : out std_logic_vector (7 
         downto 0));

end InBlock_1_DW01_inc_1;

architecture SYN_rpl of InBlock_1_DW01_inc_1 is

   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component HAX1
      port( A, B : in std_logic;  YC, YS : out std_logic);
   end component;
   
   signal carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port,
      carry_2_port : std_logic;

begin
   
   U1_1_6 : HAX1 port map( A => A(6), B => carry_6_port, YC => carry_7_port, YS
                           => SUM(6));
   U1_1_5 : HAX1 port map( A => A(5), B => carry_5_port, YC => carry_6_port, YS
                           => SUM(5));
   U1_1_4 : HAX1 port map( A => A(4), B => carry_4_port, YC => carry_5_port, YS
                           => SUM(4));
   U1_1_3 : HAX1 port map( A => A(3), B => carry_3_port, YC => carry_4_port, YS
                           => SUM(3));
   U1_1_2 : HAX1 port map( A => A(2), B => carry_2_port, YC => carry_3_port, YS
                           => SUM(2));
   U1_1_1 : HAX1 port map( A => A(1), B => A(0), YC => carry_2_port, YS => 
                           SUM(1));
   U1 : INVX2 port map( A => A(0), Y => SUM(0));
   U2 : XOR2X1 port map( A => carry_7_port, B => A(7), Y => SUM(7));

end SYN_rpl;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity InBlock_0_DW01_inc_1 is

   port( A : in std_logic_vector (7 downto 0);  SUM : out std_logic_vector (7 
         downto 0));

end InBlock_0_DW01_inc_1;

architecture SYN_rpl of InBlock_0_DW01_inc_1 is

   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component HAX1
      port( A, B : in std_logic;  YC, YS : out std_logic);
   end component;
   
   signal carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port,
      carry_2_port : std_logic;

begin
   
   U1_1_6 : HAX1 port map( A => A(6), B => carry_6_port, YC => carry_7_port, YS
                           => SUM(6));
   U1_1_5 : HAX1 port map( A => A(5), B => carry_5_port, YC => carry_6_port, YS
                           => SUM(5));
   U1_1_4 : HAX1 port map( A => A(4), B => carry_4_port, YC => carry_5_port, YS
                           => SUM(4));
   U1_1_3 : HAX1 port map( A => A(3), B => carry_3_port, YC => carry_4_port, YS
                           => SUM(3));
   U1_1_2 : HAX1 port map( A => A(2), B => carry_2_port, YC => carry_3_port, YS
                           => SUM(2));
   U1_1_1 : HAX1 port map( A => A(1), B => A(0), YC => carry_2_port, YS => 
                           SUM(1));
   U1 : INVX2 port map( A => A(0), Y => SUM(0));
   U2 : XOR2X1 port map( A => carry_7_port, B => A(7), Y => SUM(7));

end SYN_rpl;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity MEMORY_CONTROLLER_DW01_inc_9 is

   port( A : in std_logic_vector (6 downto 0);  SUM : out std_logic_vector (6 
         downto 0));

end MEMORY_CONTROLLER_DW01_inc_9;

architecture SYN_rpl of MEMORY_CONTROLLER_DW01_inc_9 is

   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component INVX1
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component HAX1
      port( A, B : in std_logic;  YC, YS : out std_logic);
   end component;
   
   signal carry_6_port, carry_5_port, carry_4_port, carry_3_port, carry_2_port 
      : std_logic;

begin
   
   U1_1_5 : HAX1 port map( A => A(5), B => carry_5_port, YC => carry_6_port, YS
                           => SUM(5));
   U1_1_4 : HAX1 port map( A => A(4), B => carry_4_port, YC => carry_5_port, YS
                           => SUM(4));
   U1_1_3 : HAX1 port map( A => A(3), B => carry_3_port, YC => carry_4_port, YS
                           => SUM(3));
   U1_1_2 : HAX1 port map( A => A(2), B => carry_2_port, YC => carry_3_port, YS
                           => SUM(2));
   U1_1_1 : HAX1 port map( A => A(1), B => A(0), YC => carry_2_port, YS => 
                           SUM(1));
   U1 : INVX1 port map( A => A(0), Y => SUM(0));
   U2 : XOR2X1 port map( A => carry_6_port, B => A(6), Y => SUM(6));

end SYN_rpl;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity MEMORY_CONTROLLER_DW01_inc_6 is

   port( A : in std_logic_vector (11 downto 0);  SUM : out std_logic_vector (11
         downto 0));

end MEMORY_CONTROLLER_DW01_inc_6;

architecture SYN_rpl of MEMORY_CONTROLLER_DW01_inc_6 is

   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component HAX1
      port( A, B : in std_logic;  YC, YS : out std_logic);
   end component;
   
   signal carry_11_port, carry_10_port, carry_9_port, carry_8_port, 
      carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port, 
      carry_2_port : std_logic;

begin
   
   U1_1_10 : HAX1 port map( A => A(10), B => carry_10_port, YC => carry_11_port
                           , YS => SUM(10));
   U1_1_9 : HAX1 port map( A => A(9), B => carry_9_port, YC => carry_10_port, 
                           YS => SUM(9));
   U1_1_8 : HAX1 port map( A => A(8), B => carry_8_port, YC => carry_9_port, YS
                           => SUM(8));
   U1_1_7 : HAX1 port map( A => A(7), B => carry_7_port, YC => carry_8_port, YS
                           => SUM(7));
   U1_1_6 : HAX1 port map( A => A(6), B => carry_6_port, YC => carry_7_port, YS
                           => SUM(6));
   U1_1_5 : HAX1 port map( A => A(5), B => carry_5_port, YC => carry_6_port, YS
                           => SUM(5));
   U1_1_4 : HAX1 port map( A => A(4), B => carry_4_port, YC => carry_5_port, YS
                           => SUM(4));
   U1_1_3 : HAX1 port map( A => A(3), B => carry_3_port, YC => carry_4_port, YS
                           => SUM(3));
   U1_1_2 : HAX1 port map( A => A(2), B => carry_2_port, YC => carry_3_port, YS
                           => SUM(2));
   U1_1_1 : HAX1 port map( A => A(1), B => A(0), YC => carry_2_port, YS => 
                           SUM(1));
   U1 : INVX2 port map( A => A(0), Y => SUM(0));
   U2 : XOR2X1 port map( A => carry_11_port, B => A(11), Y => SUM(11));

end SYN_rpl;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity MEMORY_CONTROLLER_DW01_inc_5 is

   port( A : in std_logic_vector (11 downto 0);  SUM : out std_logic_vector (11
         downto 0));

end MEMORY_CONTROLLER_DW01_inc_5;

architecture SYN_rpl of MEMORY_CONTROLLER_DW01_inc_5 is

   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component HAX1
      port( A, B : in std_logic;  YC, YS : out std_logic);
   end component;
   
   signal carry_11_port, carry_10_port, carry_9_port, carry_8_port, 
      carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port, 
      carry_2_port : std_logic;

begin
   
   U1_1_10 : HAX1 port map( A => A(10), B => carry_10_port, YC => carry_11_port
                           , YS => SUM(10));
   U1_1_9 : HAX1 port map( A => A(9), B => carry_9_port, YC => carry_10_port, 
                           YS => SUM(9));
   U1_1_8 : HAX1 port map( A => A(8), B => carry_8_port, YC => carry_9_port, YS
                           => SUM(8));
   U1_1_7 : HAX1 port map( A => A(7), B => carry_7_port, YC => carry_8_port, YS
                           => SUM(7));
   U1_1_6 : HAX1 port map( A => A(6), B => carry_6_port, YC => carry_7_port, YS
                           => SUM(6));
   U1_1_5 : HAX1 port map( A => A(5), B => carry_5_port, YC => carry_6_port, YS
                           => SUM(5));
   U1_1_4 : HAX1 port map( A => A(4), B => carry_4_port, YC => carry_5_port, YS
                           => SUM(4));
   U1_1_3 : HAX1 port map( A => A(3), B => carry_3_port, YC => carry_4_port, YS
                           => SUM(3));
   U1_1_2 : HAX1 port map( A => A(2), B => carry_2_port, YC => carry_3_port, YS
                           => SUM(2));
   U1_1_1 : HAX1 port map( A => A(1), B => A(0), YC => carry_2_port, YS => 
                           SUM(1));
   U1 : INVX2 port map( A => A(0), Y => SUM(0));
   U2 : XOR2X1 port map( A => carry_11_port, B => A(11), Y => SUM(11));

end SYN_rpl;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity MEMORY_CONTROLLER_DW01_inc_4 is

   port( A : in std_logic_vector (11 downto 0);  SUM : out std_logic_vector (11
         downto 0));

end MEMORY_CONTROLLER_DW01_inc_4;

architecture SYN_rpl of MEMORY_CONTROLLER_DW01_inc_4 is

   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component HAX1
      port( A, B : in std_logic;  YC, YS : out std_logic);
   end component;
   
   signal carry_11_port, carry_10_port, carry_9_port, carry_8_port, 
      carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port, 
      carry_2_port : std_logic;

begin
   
   U1_1_10 : HAX1 port map( A => A(10), B => carry_10_port, YC => carry_11_port
                           , YS => SUM(10));
   U1_1_9 : HAX1 port map( A => A(9), B => carry_9_port, YC => carry_10_port, 
                           YS => SUM(9));
   U1_1_8 : HAX1 port map( A => A(8), B => carry_8_port, YC => carry_9_port, YS
                           => SUM(8));
   U1_1_7 : HAX1 port map( A => A(7), B => carry_7_port, YC => carry_8_port, YS
                           => SUM(7));
   U1_1_6 : HAX1 port map( A => A(6), B => carry_6_port, YC => carry_7_port, YS
                           => SUM(6));
   U1_1_5 : HAX1 port map( A => A(5), B => carry_5_port, YC => carry_6_port, YS
                           => SUM(5));
   U1_1_4 : HAX1 port map( A => A(4), B => carry_4_port, YC => carry_5_port, YS
                           => SUM(4));
   U1_1_3 : HAX1 port map( A => A(3), B => carry_3_port, YC => carry_4_port, YS
                           => SUM(3));
   U1_1_2 : HAX1 port map( A => A(2), B => carry_2_port, YC => carry_3_port, YS
                           => SUM(2));
   U1_1_1 : HAX1 port map( A => A(1), B => A(0), YC => carry_2_port, YS => 
                           SUM(1));
   U1 : INVX2 port map( A => A(0), Y => SUM(0));
   U2 : XOR2X1 port map( A => carry_11_port, B => A(11), Y => SUM(11));

end SYN_rpl;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity MEMORY_CONTROLLER_DW01_inc_3 is

   port( A : in std_logic_vector (11 downto 0);  SUM : out std_logic_vector (11
         downto 0));

end MEMORY_CONTROLLER_DW01_inc_3;

architecture SYN_rpl of MEMORY_CONTROLLER_DW01_inc_3 is

   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component HAX1
      port( A, B : in std_logic;  YC, YS : out std_logic);
   end component;
   
   signal carry_11_port, carry_10_port, carry_9_port, carry_8_port, 
      carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port, 
      carry_2_port : std_logic;

begin
   
   U1_1_10 : HAX1 port map( A => A(10), B => carry_10_port, YC => carry_11_port
                           , YS => SUM(10));
   U1_1_9 : HAX1 port map( A => A(9), B => carry_9_port, YC => carry_10_port, 
                           YS => SUM(9));
   U1_1_8 : HAX1 port map( A => A(8), B => carry_8_port, YC => carry_9_port, YS
                           => SUM(8));
   U1_1_7 : HAX1 port map( A => A(7), B => carry_7_port, YC => carry_8_port, YS
                           => SUM(7));
   U1_1_6 : HAX1 port map( A => A(6), B => carry_6_port, YC => carry_7_port, YS
                           => SUM(6));
   U1_1_5 : HAX1 port map( A => A(5), B => carry_5_port, YC => carry_6_port, YS
                           => SUM(5));
   U1_1_4 : HAX1 port map( A => A(4), B => carry_4_port, YC => carry_5_port, YS
                           => SUM(4));
   U1_1_3 : HAX1 port map( A => A(3), B => carry_3_port, YC => carry_4_port, YS
                           => SUM(3));
   U1_1_2 : HAX1 port map( A => A(2), B => carry_2_port, YC => carry_3_port, YS
                           => SUM(2));
   U1_1_1 : HAX1 port map( A => A(1), B => A(0), YC => carry_2_port, YS => 
                           SUM(1));
   U1 : INVX2 port map( A => A(0), Y => SUM(0));
   U2 : XOR2X1 port map( A => carry_11_port, B => A(11), Y => SUM(11));

end SYN_rpl;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity MEMORY_CONTROLLER_DW01_inc_2 is

   port( A : in std_logic_vector (11 downto 0);  SUM : out std_logic_vector (11
         downto 0));

end MEMORY_CONTROLLER_DW01_inc_2;

architecture SYN_rpl of MEMORY_CONTROLLER_DW01_inc_2 is

   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component HAX1
      port( A, B : in std_logic;  YC, YS : out std_logic);
   end component;
   
   signal carry_11_port, carry_10_port, carry_9_port, carry_8_port, 
      carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port, 
      carry_2_port : std_logic;

begin
   
   U1_1_10 : HAX1 port map( A => A(10), B => carry_10_port, YC => carry_11_port
                           , YS => SUM(10));
   U1_1_9 : HAX1 port map( A => A(9), B => carry_9_port, YC => carry_10_port, 
                           YS => SUM(9));
   U1_1_8 : HAX1 port map( A => A(8), B => carry_8_port, YC => carry_9_port, YS
                           => SUM(8));
   U1_1_7 : HAX1 port map( A => A(7), B => carry_7_port, YC => carry_8_port, YS
                           => SUM(7));
   U1_1_6 : HAX1 port map( A => A(6), B => carry_6_port, YC => carry_7_port, YS
                           => SUM(6));
   U1_1_5 : HAX1 port map( A => A(5), B => carry_5_port, YC => carry_6_port, YS
                           => SUM(5));
   U1_1_4 : HAX1 port map( A => A(4), B => carry_4_port, YC => carry_5_port, YS
                           => SUM(4));
   U1_1_3 : HAX1 port map( A => A(3), B => carry_3_port, YC => carry_4_port, YS
                           => SUM(3));
   U1_1_2 : HAX1 port map( A => A(2), B => carry_2_port, YC => carry_3_port, YS
                           => SUM(2));
   U1_1_1 : HAX1 port map( A => A(1), B => A(0), YC => carry_2_port, YS => 
                           SUM(1));
   U1 : INVX2 port map( A => A(0), Y => SUM(0));
   U2 : XOR2X1 port map( A => carry_11_port, B => A(11), Y => SUM(11));

end SYN_rpl;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity MEMORY_CONTROLLER_DW01_inc_1 is

   port( A : in std_logic_vector (11 downto 0);  SUM : out std_logic_vector (11
         downto 0));

end MEMORY_CONTROLLER_DW01_inc_1;

architecture SYN_rpl of MEMORY_CONTROLLER_DW01_inc_1 is

   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component HAX1
      port( A, B : in std_logic;  YC, YS : out std_logic);
   end component;
   
   signal carry_11_port, carry_10_port, carry_9_port, carry_8_port, 
      carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port, 
      carry_2_port : std_logic;

begin
   
   U1_1_10 : HAX1 port map( A => A(10), B => carry_10_port, YC => carry_11_port
                           , YS => SUM(10));
   U1_1_9 : HAX1 port map( A => A(9), B => carry_9_port, YC => carry_10_port, 
                           YS => SUM(9));
   U1_1_8 : HAX1 port map( A => A(8), B => carry_8_port, YC => carry_9_port, YS
                           => SUM(8));
   U1_1_7 : HAX1 port map( A => A(7), B => carry_7_port, YC => carry_8_port, YS
                           => SUM(7));
   U1_1_6 : HAX1 port map( A => A(6), B => carry_6_port, YC => carry_7_port, YS
                           => SUM(6));
   U1_1_5 : HAX1 port map( A => A(5), B => carry_5_port, YC => carry_6_port, YS
                           => SUM(5));
   U1_1_4 : HAX1 port map( A => A(4), B => carry_4_port, YC => carry_5_port, YS
                           => SUM(4));
   U1_1_3 : HAX1 port map( A => A(3), B => carry_3_port, YC => carry_4_port, YS
                           => SUM(3));
   U1_1_2 : HAX1 port map( A => A(2), B => carry_2_port, YC => carry_3_port, YS
                           => SUM(2));
   U1_1_1 : HAX1 port map( A => A(1), B => A(0), YC => carry_2_port, YS => 
                           SUM(1));
   U1 : INVX2 port map( A => A(0), Y => SUM(0));
   U2 : XOR2X1 port map( A => carry_11_port, B => A(11), Y => SUM(11));

end SYN_rpl;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity MEMORY_CONTROLLER_DW01_inc_0 is

   port( A : in std_logic_vector (11 downto 0);  SUM : out std_logic_vector (11
         downto 0));

end MEMORY_CONTROLLER_DW01_inc_0;

architecture SYN_rpl of MEMORY_CONTROLLER_DW01_inc_0 is

   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component HAX1
      port( A, B : in std_logic;  YC, YS : out std_logic);
   end component;
   
   signal carry_11_port, carry_10_port, carry_9_port, carry_8_port, 
      carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port, 
      carry_2_port : std_logic;

begin
   
   U1_1_10 : HAX1 port map( A => A(10), B => carry_10_port, YC => carry_11_port
                           , YS => SUM(10));
   U1_1_9 : HAX1 port map( A => A(9), B => carry_9_port, YC => carry_10_port, 
                           YS => SUM(9));
   U1_1_8 : HAX1 port map( A => A(8), B => carry_8_port, YC => carry_9_port, YS
                           => SUM(8));
   U1_1_7 : HAX1 port map( A => A(7), B => carry_7_port, YC => carry_8_port, YS
                           => SUM(7));
   U1_1_6 : HAX1 port map( A => A(6), B => carry_6_port, YC => carry_7_port, YS
                           => SUM(6));
   U1_1_5 : HAX1 port map( A => A(5), B => carry_5_port, YC => carry_6_port, YS
                           => SUM(5));
   U1_1_4 : HAX1 port map( A => A(4), B => carry_4_port, YC => carry_5_port, YS
                           => SUM(4));
   U1_1_3 : HAX1 port map( A => A(3), B => carry_3_port, YC => carry_4_port, YS
                           => SUM(3));
   U1_1_2 : HAX1 port map( A => A(2), B => carry_2_port, YC => carry_3_port, YS
                           => SUM(2));
   U1_1_1 : HAX1 port map( A => A(1), B => A(0), YC => carry_2_port, YS => 
                           SUM(1));
   U1 : INVX2 port map( A => A(0), Y => SUM(0));
   U2 : XOR2X1 port map( A => carry_11_port, B => A(11), Y => SUM(11));

end SYN_rpl;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity SET_N_SHIFT_16_0 is

   port( CLK, RST_N, SHIFT_ENABLE, SET_ENABLE : in std_logic;  DATA_IN : in 
         std_logic_vector (15 downto 0);  SHIFT_OUT : out std_logic);

end SET_N_SHIFT_16_0;

architecture SYN_simple_set_n_shift_reg of SET_N_SHIFT_16_0 is

   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component AND2X2
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component OR2X2
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI21X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component AOI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component DFFSR
      port( D, CLK, R, S : in std_logic;  Q : out std_logic);
   end component;
   
   signal present_val_15_port, present_val_14_port, present_val_13_port, 
      present_val_12_port, present_val_11_port, present_val_10_port, 
      present_val_9_port, present_val_8_port, present_val_7_port, 
      present_val_6_port, present_val_5_port, present_val_4_port, 
      present_val_3_port, present_val_2_port, present_val_1_port, 
      present_val_0_port, next_so, n18, n19, n20, n21, n22, n23, n24, n25, n26,
      n27, n28, n29, n30, n31, n32, n33, n34, n35, n37, n69, n70, n71, n72, n73
      , n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, 
      n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, 
      n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, 
      n114, n115, n116, n117, n118, n119, n120 : std_logic;

begin
   
   present_val_reg_0_inst : DFFSR port map( D => n72, CLK => CLK, R => n22, S 
                           => n104, Q => present_val_0_port);
   present_val_reg_1_inst : DFFSR port map( D => n73, CLK => CLK, R => n22, S 
                           => n105, Q => present_val_1_port);
   present_val_reg_2_inst : DFFSR port map( D => n74, CLK => CLK, R => n22, S 
                           => n106, Q => present_val_2_port);
   present_val_reg_3_inst : DFFSR port map( D => n75, CLK => CLK, R => n22, S 
                           => n107, Q => present_val_3_port);
   present_val_reg_4_inst : DFFSR port map( D => n76, CLK => CLK, R => n22, S 
                           => n108, Q => present_val_4_port);
   present_val_reg_5_inst : DFFSR port map( D => n77, CLK => CLK, R => n22, S 
                           => n109, Q => present_val_5_port);
   present_val_reg_6_inst : DFFSR port map( D => n78, CLK => CLK, R => n22, S 
                           => n110, Q => present_val_6_port);
   present_val_reg_7_inst : DFFSR port map( D => n79, CLK => CLK, R => n22, S 
                           => n111, Q => present_val_7_port);
   present_val_reg_8_inst : DFFSR port map( D => n80, CLK => CLK, R => n22, S 
                           => n112, Q => present_val_8_port);
   present_val_reg_9_inst : DFFSR port map( D => n81, CLK => CLK, R => n22, S 
                           => n113, Q => present_val_9_port);
   present_val_reg_10_inst : DFFSR port map( D => n82, CLK => CLK, R => n22, S 
                           => n114, Q => present_val_10_port);
   present_val_reg_11_inst : DFFSR port map( D => n83, CLK => CLK, R => n22, S 
                           => n115, Q => present_val_11_port);
   present_val_reg_12_inst : DFFSR port map( D => n84, CLK => CLK, R => n22, S 
                           => n116, Q => present_val_12_port);
   present_val_reg_13_inst : DFFSR port map( D => n85, CLK => CLK, R => n22, S 
                           => n117, Q => present_val_13_port);
   present_val_reg_14_inst : DFFSR port map( D => n86, CLK => CLK, R => n22, S 
                           => n118, Q => present_val_14_port);
   present_val_reg_15_inst : DFFSR port map( D => n87, CLK => CLK, R => n22, S 
                           => n119, Q => present_val_15_port);
   so_reg : DFFSR port map( D => next_so, CLK => CLK, R => n22, S => n120, Q =>
                           SHIFT_OUT);
   n120 <= '1';
   n119 <= '1';
   n118 <= '1';
   n117 <= '1';
   n116 <= '1';
   n115 <= '1';
   n114 <= '1';
   n113 <= '1';
   n112 <= '1';
   n111 <= '1';
   n110 <= '1';
   n109 <= '1';
   n108 <= '1';
   n107 <= '1';
   n106 <= '1';
   n105 <= '1';
   n104 <= '1';
   U39 : OAI22X1 port map( A => n20, B => n70, C => SHIFT_ENABLE, D => n71, Y 
                           => next_so);
   U40 : OAI21X1 port map( A => n71, B => n18, C => n103, Y => n87);
   U41 : AOI22X1 port map( A => present_val_14_port, B => n21, C => DATA_IN(15)
                           , D => n19, Y => n103);
   U42 : OAI21X1 port map( A => n70, B => n18, C => n102, Y => n86);
   U43 : AOI22X1 port map( A => present_val_13_port, B => SHIFT_ENABLE, C => 
                           DATA_IN(14), D => n19, Y => n102);
   U44 : OAI21X1 port map( A => n18, B => n69, C => n101, Y => n85);
   U45 : AOI22X1 port map( A => present_val_12_port, B => n21, C => DATA_IN(13)
                           , D => n19, Y => n101);
   U46 : OAI21X1 port map( A => n18, B => n37, C => n100, Y => n84);
   U47 : AOI22X1 port map( A => present_val_11_port, B => SHIFT_ENABLE, C => 
                           DATA_IN(12), D => n19, Y => n100);
   U48 : OAI21X1 port map( A => n18, B => n35, C => n99, Y => n83);
   U49 : AOI22X1 port map( A => present_val_10_port, B => n21, C => DATA_IN(11)
                           , D => n19, Y => n99);
   U50 : OAI21X1 port map( A => n18, B => n34, C => n98, Y => n82);
   U51 : AOI22X1 port map( A => present_val_9_port, B => SHIFT_ENABLE, C => 
                           DATA_IN(10), D => n19, Y => n98);
   U52 : OAI21X1 port map( A => n18, B => n33, C => n97, Y => n81);
   U53 : AOI22X1 port map( A => present_val_8_port, B => n21, C => DATA_IN(9), 
                           D => n19, Y => n97);
   U54 : OAI21X1 port map( A => n18, B => n32, C => n96, Y => n80);
   U55 : AOI22X1 port map( A => present_val_7_port, B => SHIFT_ENABLE, C => 
                           DATA_IN(8), D => n19, Y => n96);
   U56 : OAI21X1 port map( A => n18, B => n31, C => n95, Y => n79);
   U57 : AOI22X1 port map( A => present_val_6_port, B => n21, C => DATA_IN(7), 
                           D => n19, Y => n95);
   U58 : OAI21X1 port map( A => n18, B => n30, C => n94, Y => n78);
   U59 : AOI22X1 port map( A => present_val_5_port, B => SHIFT_ENABLE, C => 
                           DATA_IN(6), D => n19, Y => n94);
   U60 : OAI21X1 port map( A => n18, B => n29, C => n93, Y => n77);
   U61 : AOI22X1 port map( A => present_val_4_port, B => n21, C => DATA_IN(5), 
                           D => n19, Y => n93);
   U62 : OAI21X1 port map( A => n18, B => n28, C => n92, Y => n76);
   U63 : AOI22X1 port map( A => present_val_3_port, B => SHIFT_ENABLE, C => 
                           DATA_IN(4), D => n19, Y => n92);
   U64 : OAI21X1 port map( A => n18, B => n27, C => n91, Y => n75);
   U65 : AOI22X1 port map( A => present_val_2_port, B => n21, C => DATA_IN(3), 
                           D => n19, Y => n91);
   U66 : OAI21X1 port map( A => n18, B => n26, C => n90, Y => n74);
   U67 : AOI22X1 port map( A => present_val_1_port, B => n21, C => DATA_IN(2), 
                           D => n19, Y => n90);
   U68 : OAI21X1 port map( A => n18, B => n25, C => n89, Y => n73);
   U69 : AOI22X1 port map( A => present_val_0_port, B => n21, C => DATA_IN(1), 
                           D => n19, Y => n89);
   U70 : OAI21X1 port map( A => n18, B => n24, C => n88, Y => n72);
   U71 : NAND2X1 port map( A => DATA_IN(0), B => n19, Y => n88);
   U20 : OR2X2 port map( A => SET_ENABLE, B => n21, Y => n18);
   U21 : AND2X2 port map( A => n18, B => n20, Y => n19);
   U22 : INVX2 port map( A => n20, Y => n21);
   U23 : INVX2 port map( A => SHIFT_ENABLE, Y => n20);
   U24 : INVX2 port map( A => n23, Y => n22);
   U25 : INVX2 port map( A => RST_N, Y => n23);
   U26 : INVX2 port map( A => present_val_0_port, Y => n24);
   U27 : INVX2 port map( A => present_val_1_port, Y => n25);
   U28 : INVX2 port map( A => present_val_2_port, Y => n26);
   U29 : INVX2 port map( A => present_val_3_port, Y => n27);
   U30 : INVX2 port map( A => present_val_4_port, Y => n28);
   U31 : INVX2 port map( A => present_val_5_port, Y => n29);
   U32 : INVX2 port map( A => present_val_6_port, Y => n30);
   U33 : INVX2 port map( A => present_val_7_port, Y => n31);
   U34 : INVX2 port map( A => present_val_8_port, Y => n32);
   U35 : INVX2 port map( A => present_val_9_port, Y => n33);
   U36 : INVX2 port map( A => present_val_10_port, Y => n34);
   U37 : INVX2 port map( A => present_val_11_port, Y => n35);
   U38 : INVX2 port map( A => present_val_12_port, Y => n37);
   U72 : INVX2 port map( A => present_val_13_port, Y => n69);
   U73 : INVX2 port map( A => present_val_14_port, Y => n70);
   U74 : INVX2 port map( A => present_val_15_port, Y => n71);

end SYN_simple_set_n_shift_reg;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity SHIFT_REG_16_2 is

   port( CLK, RST_N, SHIFT_ENABLE, D_ORIG : in std_logic;  RCV_DATA : out 
         std_logic_vector (15 downto 0));

end SHIFT_REG_16_2;

architecture SYN_simple_shift_reg of SHIFT_REG_16_2 is

   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI21X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component DFFSR
      port( D, CLK, R, S : in std_logic;  Q : out std_logic);
   end component;
   
   signal RCV_DATA_15_port, RCV_DATA_14_port, RCV_DATA_13_port, 
      RCV_DATA_12_port, RCV_DATA_11_port, RCV_DATA_10_port, RCV_DATA_9_port, 
      RCV_DATA_8_port, RCV_DATA_7_port, RCV_DATA_6_port, RCV_DATA_5_port, 
      RCV_DATA_4_port, RCV_DATA_3_port, RCV_DATA_2_port, RCV_DATA_1_port, 
      RCV_DATA_0_port, n1, n2, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14,
      n15, n16, n17, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62
      , n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, 
      n77, n78, n79, n80, n81, n82, n83, n84 : std_logic;

begin
   RCV_DATA <= ( RCV_DATA_15_port, RCV_DATA_14_port, RCV_DATA_13_port, 
      RCV_DATA_12_port, RCV_DATA_11_port, RCV_DATA_10_port, RCV_DATA_9_port, 
      RCV_DATA_8_port, RCV_DATA_7_port, RCV_DATA_6_port, RCV_DATA_5_port, 
      RCV_DATA_4_port, RCV_DATA_3_port, RCV_DATA_2_port, RCV_DATA_1_port, 
      RCV_DATA_0_port );
   
   present_val_reg_0_inst : DFFSR port map( D => n51, CLK => CLK, R => RST_N, S
                           => n52, Q => RCV_DATA_0_port);
   present_val_reg_1_inst : DFFSR port map( D => n53, CLK => CLK, R => RST_N, S
                           => n54, Q => RCV_DATA_1_port);
   present_val_reg_2_inst : DFFSR port map( D => n55, CLK => CLK, R => RST_N, S
                           => n56, Q => RCV_DATA_2_port);
   present_val_reg_3_inst : DFFSR port map( D => n57, CLK => CLK, R => RST_N, S
                           => n58, Q => RCV_DATA_3_port);
   present_val_reg_4_inst : DFFSR port map( D => n59, CLK => CLK, R => RST_N, S
                           => n60, Q => RCV_DATA_4_port);
   present_val_reg_5_inst : DFFSR port map( D => n61, CLK => CLK, R => RST_N, S
                           => n62, Q => RCV_DATA_5_port);
   present_val_reg_6_inst : DFFSR port map( D => n63, CLK => CLK, R => RST_N, S
                           => n64, Q => RCV_DATA_6_port);
   present_val_reg_7_inst : DFFSR port map( D => n65, CLK => CLK, R => RST_N, S
                           => n66, Q => RCV_DATA_7_port);
   present_val_reg_8_inst : DFFSR port map( D => n67, CLK => CLK, R => RST_N, S
                           => n68, Q => RCV_DATA_8_port);
   present_val_reg_9_inst : DFFSR port map( D => n69, CLK => CLK, R => RST_N, S
                           => n70, Q => RCV_DATA_9_port);
   present_val_reg_10_inst : DFFSR port map( D => n71, CLK => CLK, R => RST_N, 
                           S => n72, Q => RCV_DATA_10_port);
   present_val_reg_11_inst : DFFSR port map( D => n73, CLK => CLK, R => RST_N, 
                           S => n74, Q => RCV_DATA_11_port);
   present_val_reg_12_inst : DFFSR port map( D => n75, CLK => CLK, R => RST_N, 
                           S => n76, Q => RCV_DATA_12_port);
   present_val_reg_13_inst : DFFSR port map( D => n77, CLK => CLK, R => RST_N, 
                           S => n78, Q => RCV_DATA_13_port);
   present_val_reg_14_inst : DFFSR port map( D => n79, CLK => CLK, R => RST_N, 
                           S => n80, Q => RCV_DATA_14_port);
   present_val_reg_15_inst : DFFSR port map( D => n81, CLK => CLK, R => RST_N, 
                           S => n82, Q => RCV_DATA_15_port);
   U2 : OAI21X1 port map( A => n16, B => n17, C => n84, Y => n81);
   U3 : NAND2X1 port map( A => RCV_DATA_15_port, B => n17, Y => n84);
   U4 : OAI22X1 port map( A => SHIFT_ENABLE, B => n16, C => n17, D => n15, Y =>
                           n79);
   U6 : OAI22X1 port map( A => SHIFT_ENABLE, B => n15, C => n17, D => n14, Y =>
                           n77);
   U8 : OAI22X1 port map( A => SHIFT_ENABLE, B => n14, C => n17, D => n13, Y =>
                           n75);
   U10 : OAI22X1 port map( A => SHIFT_ENABLE, B => n13, C => n17, D => n12, Y 
                           => n73);
   U12 : OAI22X1 port map( A => n17, B => n11, C => SHIFT_ENABLE, D => n12, Y 
                           => n71);
   U14 : OAI22X1 port map( A => SHIFT_ENABLE, B => n11, C => n17, D => n10, Y 
                           => n69);
   U16 : OAI22X1 port map( A => SHIFT_ENABLE, B => n10, C => n17, D => n9, Y =>
                           n67);
   U18 : OAI22X1 port map( A => SHIFT_ENABLE, B => n9, C => n17, D => n8, Y => 
                           n65);
   U20 : OAI22X1 port map( A => SHIFT_ENABLE, B => n8, C => n17, D => n7, Y => 
                           n63);
   U22 : OAI22X1 port map( A => SHIFT_ENABLE, B => n7, C => n17, D => n6, Y => 
                           n61);
   U24 : OAI22X1 port map( A => SHIFT_ENABLE, B => n6, C => n17, D => n5, Y => 
                           n59);
   U26 : OAI22X1 port map( A => SHIFT_ENABLE, B => n5, C => n17, D => n4, Y => 
                           n57);
   U28 : OAI22X1 port map( A => SHIFT_ENABLE, B => n4, C => n17, D => n2, Y => 
                           n55);
   U30 : OAI22X1 port map( A => SHIFT_ENABLE, B => n2, C => n17, D => n1, Y => 
                           n53);
   U33 : OAI21X1 port map( A => SHIFT_ENABLE, B => n1, C => n83, Y => n51);
   U34 : NAND2X1 port map( A => D_ORIG, B => SHIFT_ENABLE, Y => n83);
   n82 <= '1';
   n80 <= '1';
   n78 <= '1';
   n76 <= '1';
   n74 <= '1';
   n72 <= '1';
   n70 <= '1';
   n68 <= '1';
   n66 <= '1';
   n64 <= '1';
   n62 <= '1';
   n60 <= '1';
   n58 <= '1';
   n56 <= '1';
   n54 <= '1';
   n52 <= '1';
   U5 : INVX2 port map( A => SHIFT_ENABLE, Y => n17);
   U7 : INVX2 port map( A => RCV_DATA_0_port, Y => n1);
   U9 : INVX2 port map( A => RCV_DATA_1_port, Y => n2);
   U11 : INVX2 port map( A => RCV_DATA_2_port, Y => n4);
   U13 : INVX2 port map( A => RCV_DATA_3_port, Y => n5);
   U15 : INVX2 port map( A => RCV_DATA_4_port, Y => n6);
   U17 : INVX2 port map( A => RCV_DATA_5_port, Y => n7);
   U19 : INVX2 port map( A => RCV_DATA_6_port, Y => n8);
   U21 : INVX2 port map( A => RCV_DATA_7_port, Y => n9);
   U23 : INVX2 port map( A => RCV_DATA_8_port, Y => n10);
   U25 : INVX2 port map( A => RCV_DATA_9_port, Y => n11);
   U27 : INVX2 port map( A => RCV_DATA_10_port, Y => n12);
   U29 : INVX2 port map( A => RCV_DATA_11_port, Y => n13);
   U31 : INVX2 port map( A => RCV_DATA_12_port, Y => n14);
   U32 : INVX2 port map( A => RCV_DATA_13_port, Y => n15);
   U35 : INVX2 port map( A => RCV_DATA_14_port, Y => n16);

end SYN_simple_shift_reg;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity SHIFT_REG_16_1 is

   port( CLK, RST_N, SHIFT_ENABLE, D_ORIG : in std_logic;  RCV_DATA : out 
         std_logic_vector (15 downto 0));

end SHIFT_REG_16_1;

architecture SYN_simple_shift_reg of SHIFT_REG_16_1 is

   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component BUFX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI21X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component DFFSR
      port( D, CLK, R, S : in std_logic;  Q : out std_logic);
   end component;
   
   signal RCV_DATA_15_port, RCV_DATA_14_port, RCV_DATA_13_port, 
      RCV_DATA_12_port, RCV_DATA_11_port, RCV_DATA_10_port, RCV_DATA_9_port, 
      RCV_DATA_8_port, RCV_DATA_7_port, RCV_DATA_6_port, RCV_DATA_5_port, 
      RCV_DATA_4_port, RCV_DATA_3_port, RCV_DATA_2_port, RCV_DATA_1_port, 
      RCV_DATA_0_port, n1, n2, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14,
      n15, n16, n17, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62
      , n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, 
      n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88 : std_logic;

begin
   RCV_DATA <= ( RCV_DATA_15_port, RCV_DATA_14_port, RCV_DATA_13_port, 
      RCV_DATA_12_port, RCV_DATA_11_port, RCV_DATA_10_port, RCV_DATA_9_port, 
      RCV_DATA_8_port, RCV_DATA_7_port, RCV_DATA_6_port, RCV_DATA_5_port, 
      RCV_DATA_4_port, RCV_DATA_3_port, RCV_DATA_2_port, RCV_DATA_1_port, 
      RCV_DATA_0_port );
   
   present_val_reg_0_inst : DFFSR port map( D => n55, CLK => CLK, R => RST_N, S
                           => n56, Q => RCV_DATA_0_port);
   present_val_reg_1_inst : DFFSR port map( D => n57, CLK => CLK, R => RST_N, S
                           => n58, Q => RCV_DATA_1_port);
   present_val_reg_2_inst : DFFSR port map( D => n59, CLK => CLK, R => RST_N, S
                           => n60, Q => RCV_DATA_2_port);
   present_val_reg_3_inst : DFFSR port map( D => n61, CLK => CLK, R => RST_N, S
                           => n62, Q => RCV_DATA_3_port);
   present_val_reg_4_inst : DFFSR port map( D => n63, CLK => CLK, R => RST_N, S
                           => n64, Q => RCV_DATA_4_port);
   present_val_reg_5_inst : DFFSR port map( D => n65, CLK => CLK, R => RST_N, S
                           => n66, Q => RCV_DATA_5_port);
   present_val_reg_6_inst : DFFSR port map( D => n67, CLK => CLK, R => RST_N, S
                           => n68, Q => RCV_DATA_6_port);
   present_val_reg_7_inst : DFFSR port map( D => n69, CLK => CLK, R => RST_N, S
                           => n70, Q => RCV_DATA_7_port);
   present_val_reg_8_inst : DFFSR port map( D => n71, CLK => CLK, R => RST_N, S
                           => n72, Q => RCV_DATA_8_port);
   present_val_reg_9_inst : DFFSR port map( D => n73, CLK => CLK, R => RST_N, S
                           => n74, Q => RCV_DATA_9_port);
   present_val_reg_10_inst : DFFSR port map( D => n75, CLK => CLK, R => RST_N, 
                           S => n76, Q => RCV_DATA_10_port);
   present_val_reg_11_inst : DFFSR port map( D => n77, CLK => CLK, R => RST_N, 
                           S => n78, Q => RCV_DATA_11_port);
   present_val_reg_12_inst : DFFSR port map( D => n79, CLK => CLK, R => RST_N, 
                           S => n80, Q => RCV_DATA_12_port);
   present_val_reg_13_inst : DFFSR port map( D => n81, CLK => CLK, R => RST_N, 
                           S => n82, Q => RCV_DATA_13_port);
   present_val_reg_14_inst : DFFSR port map( D => n83, CLK => CLK, R => RST_N, 
                           S => n84, Q => RCV_DATA_14_port);
   present_val_reg_15_inst : DFFSR port map( D => n85, CLK => CLK, R => RST_N, 
                           S => n86, Q => RCV_DATA_15_port);
   U2 : OAI21X1 port map( A => n54, B => n6, C => n88, Y => n85);
   U3 : NAND2X1 port map( A => RCV_DATA_15_port, B => n6, Y => n88);
   U4 : OAI22X1 port map( A => n1, B => n54, C => n6, D => n53, Y => n83);
   U6 : OAI22X1 port map( A => n1, B => n53, C => n6, D => n52, Y => n81);
   U8 : OAI22X1 port map( A => n4, B => n52, C => n6, D => n51, Y => n79);
   U10 : OAI22X1 port map( A => n2, B => n51, C => n6, D => n17, Y => n77);
   U12 : OAI22X1 port map( A => n6, B => n16, C => n1, D => n17, Y => n75);
   U14 : OAI22X1 port map( A => n2, B => n16, C => n6, D => n15, Y => n73);
   U16 : OAI22X1 port map( A => n2, B => n15, C => n6, D => n14, Y => n71);
   U18 : OAI22X1 port map( A => n4, B => n14, C => n6, D => n13, Y => n69);
   U20 : OAI22X1 port map( A => n4, B => n13, C => n6, D => n12, Y => n67);
   U22 : OAI22X1 port map( A => n4, B => n12, C => n6, D => n11, Y => n65);
   U24 : OAI22X1 port map( A => n4, B => n11, C => n6, D => n10, Y => n63);
   U26 : OAI22X1 port map( A => n4, B => n10, C => n6, D => n9, Y => n61);
   U28 : OAI22X1 port map( A => n4, B => n9, C => n6, D => n8, Y => n59);
   U30 : OAI22X1 port map( A => n5, B => n8, C => n6, D => n7, Y => n57);
   U33 : OAI21X1 port map( A => n5, B => n7, C => n87, Y => n55);
   U34 : NAND2X1 port map( A => D_ORIG, B => n1, Y => n87);
   n86 <= '1';
   n84 <= '1';
   n82 <= '1';
   n80 <= '1';
   n78 <= '1';
   n76 <= '1';
   n74 <= '1';
   n72 <= '1';
   n70 <= '1';
   n68 <= '1';
   n66 <= '1';
   n64 <= '1';
   n62 <= '1';
   n60 <= '1';
   n58 <= '1';
   n56 <= '1';
   U5 : INVX2 port map( A => n1, Y => n6);
   U7 : BUFX2 port map( A => SHIFT_ENABLE, Y => n1);
   U9 : BUFX2 port map( A => SHIFT_ENABLE, Y => n2);
   U11 : BUFX2 port map( A => SHIFT_ENABLE, Y => n4);
   U13 : BUFX2 port map( A => SHIFT_ENABLE, Y => n5);
   U15 : INVX2 port map( A => RCV_DATA_0_port, Y => n7);
   U17 : INVX2 port map( A => RCV_DATA_1_port, Y => n8);
   U19 : INVX2 port map( A => RCV_DATA_2_port, Y => n9);
   U21 : INVX2 port map( A => RCV_DATA_3_port, Y => n10);
   U23 : INVX2 port map( A => RCV_DATA_4_port, Y => n11);
   U25 : INVX2 port map( A => RCV_DATA_5_port, Y => n12);
   U27 : INVX2 port map( A => RCV_DATA_6_port, Y => n13);
   U29 : INVX2 port map( A => RCV_DATA_7_port, Y => n14);
   U31 : INVX2 port map( A => RCV_DATA_8_port, Y => n15);
   U32 : INVX2 port map( A => RCV_DATA_9_port, Y => n16);
   U35 : INVX2 port map( A => RCV_DATA_10_port, Y => n17);
   U52 : INVX2 port map( A => RCV_DATA_11_port, Y => n51);
   U53 : INVX2 port map( A => RCV_DATA_12_port, Y => n52);
   U54 : INVX2 port map( A => RCV_DATA_13_port, Y => n53);
   U55 : INVX2 port map( A => RCV_DATA_14_port, Y => n54);

end SYN_simple_shift_reg;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity SHIFT_REG_16_0 is

   port( CLK, RST_N, SHIFT_ENABLE, D_ORIG : in std_logic;  RCV_DATA : out 
         std_logic_vector (15 downto 0));

end SHIFT_REG_16_0;

architecture SYN_simple_shift_reg of SHIFT_REG_16_0 is

   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI21X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component DFFSR
      port( D, CLK, R, S : in std_logic;  Q : out std_logic);
   end component;
   
   signal RCV_DATA_15_port, RCV_DATA_14_port, RCV_DATA_13_port, 
      RCV_DATA_12_port, RCV_DATA_11_port, RCV_DATA_10_port, RCV_DATA_9_port, 
      RCV_DATA_8_port, RCV_DATA_7_port, RCV_DATA_6_port, RCV_DATA_5_port, 
      RCV_DATA_4_port, RCV_DATA_3_port, RCV_DATA_2_port, RCV_DATA_1_port, 
      RCV_DATA_0_port, n1, n2, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14,
      n15, n16, n17, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62
      , n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, 
      n77, n78, n79, n80, n81, n82, n83, n84 : std_logic;

begin
   RCV_DATA <= ( RCV_DATA_15_port, RCV_DATA_14_port, RCV_DATA_13_port, 
      RCV_DATA_12_port, RCV_DATA_11_port, RCV_DATA_10_port, RCV_DATA_9_port, 
      RCV_DATA_8_port, RCV_DATA_7_port, RCV_DATA_6_port, RCV_DATA_5_port, 
      RCV_DATA_4_port, RCV_DATA_3_port, RCV_DATA_2_port, RCV_DATA_1_port, 
      RCV_DATA_0_port );
   
   present_val_reg_0_inst : DFFSR port map( D => n51, CLK => CLK, R => RST_N, S
                           => n52, Q => RCV_DATA_0_port);
   present_val_reg_1_inst : DFFSR port map( D => n53, CLK => CLK, R => RST_N, S
                           => n54, Q => RCV_DATA_1_port);
   present_val_reg_2_inst : DFFSR port map( D => n55, CLK => CLK, R => RST_N, S
                           => n56, Q => RCV_DATA_2_port);
   present_val_reg_3_inst : DFFSR port map( D => n57, CLK => CLK, R => RST_N, S
                           => n58, Q => RCV_DATA_3_port);
   present_val_reg_4_inst : DFFSR port map( D => n59, CLK => CLK, R => RST_N, S
                           => n60, Q => RCV_DATA_4_port);
   present_val_reg_5_inst : DFFSR port map( D => n61, CLK => CLK, R => RST_N, S
                           => n62, Q => RCV_DATA_5_port);
   present_val_reg_6_inst : DFFSR port map( D => n63, CLK => CLK, R => RST_N, S
                           => n64, Q => RCV_DATA_6_port);
   present_val_reg_7_inst : DFFSR port map( D => n65, CLK => CLK, R => RST_N, S
                           => n66, Q => RCV_DATA_7_port);
   present_val_reg_8_inst : DFFSR port map( D => n67, CLK => CLK, R => RST_N, S
                           => n68, Q => RCV_DATA_8_port);
   present_val_reg_9_inst : DFFSR port map( D => n69, CLK => CLK, R => RST_N, S
                           => n70, Q => RCV_DATA_9_port);
   present_val_reg_10_inst : DFFSR port map( D => n71, CLK => CLK, R => RST_N, 
                           S => n72, Q => RCV_DATA_10_port);
   present_val_reg_11_inst : DFFSR port map( D => n73, CLK => CLK, R => RST_N, 
                           S => n74, Q => RCV_DATA_11_port);
   present_val_reg_12_inst : DFFSR port map( D => n75, CLK => CLK, R => RST_N, 
                           S => n76, Q => RCV_DATA_12_port);
   present_val_reg_13_inst : DFFSR port map( D => n77, CLK => CLK, R => RST_N, 
                           S => n78, Q => RCV_DATA_13_port);
   present_val_reg_14_inst : DFFSR port map( D => n79, CLK => CLK, R => RST_N, 
                           S => n80, Q => RCV_DATA_14_port);
   present_val_reg_15_inst : DFFSR port map( D => n81, CLK => CLK, R => RST_N, 
                           S => n82, Q => RCV_DATA_15_port);
   U2 : OAI21X1 port map( A => n16, B => n17, C => n84, Y => n81);
   U3 : NAND2X1 port map( A => RCV_DATA_15_port, B => n17, Y => n84);
   U4 : OAI22X1 port map( A => SHIFT_ENABLE, B => n16, C => n17, D => n15, Y =>
                           n79);
   U6 : OAI22X1 port map( A => SHIFT_ENABLE, B => n15, C => n17, D => n14, Y =>
                           n77);
   U8 : OAI22X1 port map( A => SHIFT_ENABLE, B => n14, C => n17, D => n13, Y =>
                           n75);
   U10 : OAI22X1 port map( A => SHIFT_ENABLE, B => n13, C => n17, D => n12, Y 
                           => n73);
   U12 : OAI22X1 port map( A => n17, B => n11, C => SHIFT_ENABLE, D => n12, Y 
                           => n71);
   U14 : OAI22X1 port map( A => SHIFT_ENABLE, B => n11, C => n17, D => n10, Y 
                           => n69);
   U16 : OAI22X1 port map( A => SHIFT_ENABLE, B => n10, C => n17, D => n9, Y =>
                           n67);
   U18 : OAI22X1 port map( A => SHIFT_ENABLE, B => n9, C => n17, D => n8, Y => 
                           n65);
   U20 : OAI22X1 port map( A => SHIFT_ENABLE, B => n8, C => n17, D => n7, Y => 
                           n63);
   U22 : OAI22X1 port map( A => SHIFT_ENABLE, B => n7, C => n17, D => n6, Y => 
                           n61);
   U24 : OAI22X1 port map( A => SHIFT_ENABLE, B => n6, C => n17, D => n5, Y => 
                           n59);
   U26 : OAI22X1 port map( A => SHIFT_ENABLE, B => n5, C => n17, D => n4, Y => 
                           n57);
   U28 : OAI22X1 port map( A => SHIFT_ENABLE, B => n4, C => n17, D => n2, Y => 
                           n55);
   U30 : OAI22X1 port map( A => SHIFT_ENABLE, B => n2, C => n17, D => n1, Y => 
                           n53);
   U33 : OAI21X1 port map( A => SHIFT_ENABLE, B => n1, C => n83, Y => n51);
   U34 : NAND2X1 port map( A => D_ORIG, B => SHIFT_ENABLE, Y => n83);
   n82 <= '1';
   n80 <= '1';
   n78 <= '1';
   n76 <= '1';
   n74 <= '1';
   n72 <= '1';
   n70 <= '1';
   n68 <= '1';
   n66 <= '1';
   n64 <= '1';
   n62 <= '1';
   n60 <= '1';
   n58 <= '1';
   n56 <= '1';
   n54 <= '1';
   n52 <= '1';
   U5 : INVX2 port map( A => SHIFT_ENABLE, Y => n17);
   U7 : INVX2 port map( A => RCV_DATA_0_port, Y => n1);
   U9 : INVX2 port map( A => RCV_DATA_1_port, Y => n2);
   U11 : INVX2 port map( A => RCV_DATA_2_port, Y => n4);
   U13 : INVX2 port map( A => RCV_DATA_3_port, Y => n5);
   U15 : INVX2 port map( A => RCV_DATA_4_port, Y => n6);
   U17 : INVX2 port map( A => RCV_DATA_5_port, Y => n7);
   U19 : INVX2 port map( A => RCV_DATA_6_port, Y => n8);
   U21 : INVX2 port map( A => RCV_DATA_7_port, Y => n9);
   U23 : INVX2 port map( A => RCV_DATA_8_port, Y => n10);
   U25 : INVX2 port map( A => RCV_DATA_9_port, Y => n11);
   U27 : INVX2 port map( A => RCV_DATA_10_port, Y => n12);
   U29 : INVX2 port map( A => RCV_DATA_11_port, Y => n13);
   U31 : INVX2 port map( A => RCV_DATA_12_port, Y => n14);
   U32 : INVX2 port map( A => RCV_DATA_13_port, Y => n15);
   U35 : INVX2 port map( A => RCV_DATA_14_port, Y => n16);

end SYN_simple_shift_reg;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity InBlock_0 is

   port( RST, BCLK, EN, SYNC, STRB : in std_logic;  DataReadyB, DataReadyW, 
         Shift1En, Shift2En, ZeroPad : out std_logic);

end InBlock_0;

architecture SYN_A_InBlock of InBlock_0 is

   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND3X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component NOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component XNOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component AND2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component INVX4
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component HAX1
      port( A, B : in std_logic;  YC, YS : out std_logic);
   end component;
   
   component InBlock_0_DW01_inc_1
      port( A : in std_logic_vector (7 downto 0);  SUM : out std_logic_vector 
            (7 downto 0));
   end component;
   
   component NAND2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component NOR3X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI21X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component AOI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component AOI21X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component OR2X2
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component AND2X2
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component LATCH
      port( CLK, D : in std_logic;  Q : out std_logic);
   end component;
   
   component DFFSR
      port( D, CLK, R, S : in std_logic;  Q : out std_logic);
   end component;
   
   signal bitCount_7_port, bitCount_6_port, bitCount_5_port, bitCount_4_port, 
      bitCount_3_port, bitCount_2_port, bitCount_1_port, bitCount_0_port, 
      wordCount_4_port, wordCount_3_port, wordCount_2_port, wordCount_1_port, 
      wordCount_0_port, genCount_3_port, genCount_2_port, genCount_1_port, 
      genCount_0_port, state_3_port, state_2_port, state_1_port, state_0_port, 
      state2_1_port, state2_0_port, nextState_3_port, nextState_2_port, 
      nextState_1_port, nextState_0_port, nextState2_1_port, nextState2_0_port,
      nextWordCount_4_port, nextWordCount_3_port, nextWordCount_2_port, 
      nextWordCount_1_port, nextWordCount_0_port, N109, N110, N111, N112, N113,
      N114, N115, N116, N130, N131, N132, N133, N134, N154, N155, N156, N157, 
      N158, N201, N202, N203, N204, N304, N305, N306, N307, N348, N356, 
      add_100_aco_carry_1_port, add_100_aco_carry_2_port, 
      add_100_aco_carry_3_port, add_100_aco_carry_4_port, add_100_aco_B_0_port,
      add_89_aco_carry_1_port, add_89_aco_carry_2_port, add_89_aco_carry_3_port
      , add_89_aco_carry_4_port, add_89_aco_B_0_port, r98_carry_2_port, 
      r98_carry_3_port, r98_carry_4_port, n1, n2, n3, n4, n5, n6, n29, n31, n32
      , n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, 
      n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61
      , n62, n63, n64, n65, n66, n67, n68, n69, n70, n72, n74, n75, n185, n186,
      n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, 
      n199, n200, n201_port, n202_port, n203_port, n204_port, n205, n206, n207,
      n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, 
      n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, 
      n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, 
      n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, 
      n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, 
      n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, 
      n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, 
      n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, 
      n304_port, n305_port, n306_port, n307_port, n308, n309, n310, n311, n312,
      n313, n314, n315, n316 : std_logic;

begin
   
   state_reg_0_inst : DFFSR port map( D => nextState_0_port, CLK => BCLK, R => 
                           n75, S => n294, Q => state_0_port);
   genCount_reg_2_inst : DFFSR port map( D => n195, CLK => BCLK, R => n75, S =>
                           n295, Q => genCount_2_port);
   genCount_reg_3_inst : DFFSR port map( D => n196, CLK => BCLK, R => n75, S =>
                           n296, Q => genCount_3_port);
   state_reg_2_inst : DFFSR port map( D => nextState_2_port, CLK => BCLK, R => 
                           n75, S => n297, Q => state_2_port);
   genCount_reg_0_inst : DFFSR port map( D => n193, CLK => BCLK, R => n75, S =>
                           n298, Q => genCount_0_port);
   genCount_reg_1_inst : DFFSR port map( D => n194, CLK => BCLK, R => n75, S =>
                           n299, Q => genCount_1_port);
   state_reg_1_inst : DFFSR port map( D => nextState_1_port, CLK => BCLK, R => 
                           n75, S => n300, Q => state_1_port);
   wordCount_reg_0_inst : DFFSR port map( D => nextWordCount_0_port, CLK => 
                           BCLK, R => n75, S => n301, Q => wordCount_0_port);
   state_reg_3_inst : DFFSR port map( D => nextState_3_port, CLK => BCLK, R => 
                           n75, S => n302, Q => state_3_port);
   bitCount_reg_7_inst : DFFSR port map( D => n192, CLK => BCLK, R => n75, S =>
                           n303, Q => bitCount_7_port);
   bitCount_reg_0_inst : DFFSR port map( D => n185, CLK => BCLK, R => n75, S =>
                           n304_port, Q => bitCount_0_port);
   bitCount_reg_1_inst : DFFSR port map( D => n186, CLK => BCLK, R => n75, S =>
                           n305_port, Q => bitCount_1_port);
   bitCount_reg_2_inst : DFFSR port map( D => n187, CLK => BCLK, R => n75, S =>
                           n306_port, Q => bitCount_2_port);
   bitCount_reg_3_inst : DFFSR port map( D => n188, CLK => BCLK, R => n75, S =>
                           n307_port, Q => bitCount_3_port);
   bitCount_reg_4_inst : DFFSR port map( D => n189, CLK => BCLK, R => n75, S =>
                           n308, Q => bitCount_4_port);
   bitCount_reg_5_inst : DFFSR port map( D => n190, CLK => BCLK, R => n75, S =>
                           n309, Q => bitCount_5_port);
   bitCount_reg_6_inst : DFFSR port map( D => n191, CLK => BCLK, R => n75, S =>
                           n310, Q => bitCount_6_port);
   wordCount_reg_4_inst : DFFSR port map( D => nextWordCount_4_port, CLK => 
                           BCLK, R => n75, S => n311, Q => wordCount_4_port);
   wordCount_reg_3_inst : DFFSR port map( D => nextWordCount_3_port, CLK => 
                           BCLK, R => n75, S => n312, Q => wordCount_3_port);
   wordCount_reg_1_inst : DFFSR port map( D => nextWordCount_1_port, CLK => 
                           BCLK, R => n75, S => n313, Q => wordCount_1_port);
   wordCount_reg_2_inst : DFFSR port map( D => nextWordCount_2_port, CLK => 
                           BCLK, R => n75, S => n314, Q => wordCount_2_port);
   state2_reg_1_inst : DFFSR port map( D => nextState2_1_port, CLK => BCLK, R 
                           => n75, S => n315, Q => state2_1_port);
   state2_reg_0_inst : DFFSR port map( D => nextState2_0_port, CLK => BCLK, R 
                           => n75, S => n316, Q => state2_0_port);
   ZeroPad_reg : LATCH port map( CLK => N307, D => n41, Q => ZeroPad);
   Shift1En_reg : LATCH port map( CLK => N304, D => N305, Q => Shift1En);
   Shift2En_reg : LATCH port map( CLK => N304, D => N306, Q => Shift2En);
   n316 <= '1';
   n315 <= '1';
   n314 <= '1';
   n313 <= '1';
   n312 <= '1';
   n311 <= '1';
   n310 <= '1';
   n309 <= '1';
   n308 <= '1';
   n307_port <= '1';
   n306_port <= '1';
   n305_port <= '1';
   n304_port <= '1';
   n303 <= '1';
   n302 <= '1';
   n301 <= '1';
   n300 <= '1';
   n299 <= '1';
   n298 <= '1';
   n297 <= '1';
   n296 <= '1';
   n295 <= '1';
   n294 <= '1';
   U30 : AND2X2 port map( A => add_89_aco_B_0_port, B => n275, Y => n291);
   U31 : OR2X2 port map( A => n255, B => n254, Y => nextState_0_port);
   U32 : OR2X2 port map( A => n46, B => N305, Y => n200);
   U78 : NAND2X1 port map( A => n293, B => n292, Y => nextWordCount_4_port);
   U79 : AOI22X1 port map( A => N204, B => n291, C => wordCount_4_port, D => 
                           n290, Y => n292);
   U80 : AOI22X1 port map( A => N158, B => n46, C => N134, D => n44, Y => n293)
                           ;
   U81 : NAND2X1 port map( A => n289, B => n288, Y => nextWordCount_3_port);
   U82 : AOI22X1 port map( A => N203, B => n291, C => wordCount_3_port, D => 
                           n290, Y => n288);
   U83 : AOI22X1 port map( A => N157, B => n46, C => N133, D => n44, Y => n289)
                           ;
   U84 : NAND2X1 port map( A => n287, B => n286, Y => nextWordCount_2_port);
   U85 : AOI22X1 port map( A => N202, B => n291, C => wordCount_2_port, D => 
                           n290, Y => n286);
   U86 : AOI22X1 port map( A => N156, B => n46, C => N132, D => n44, Y => n287)
                           ;
   U87 : NAND2X1 port map( A => n285, B => n284, Y => nextWordCount_1_port);
   U88 : AOI22X1 port map( A => N201, B => n291, C => wordCount_1_port, D => 
                           n290, Y => n284);
   U89 : AOI22X1 port map( A => N155, B => n46, C => N131, D => n44, Y => n285)
                           ;
   U90 : NAND2X1 port map( A => n283, B => n282, Y => nextWordCount_0_port);
   U91 : AOI22X1 port map( A => n1, B => n291, C => wordCount_0_port, D => n290
                           , Y => n282);
   U92 : NAND3X1 port map( A => n281, B => n280, C => n279, Y => n290);
   U93 : NOR2X1 port map( A => n41, B => n278, Y => n279);
   U94 : NOR2X1 port map( A => n277, B => n47, Y => n281);
   U95 : AOI22X1 port map( A => N154, B => n46, C => N130, D => n44, Y => n283)
                           ;
   U96 : OAI22X1 port map( A => add_89_aco_B_0_port, B => n274, C => n56, D => 
                           n273, Y => nextState_3_port);
   U97 : NAND3X1 port map( A => n272, B => n280, C => n271, Y => 
                           nextState_2_port);
   U98 : NOR2X1 port map( A => n270, B => n269, Y => n271);
   U99 : OAI21X1 port map( A => n268, B => n267, C => n266, Y => n269);
   U100 : OAI21X1 port map( A => n265, B => n264, C => n41, Y => n266);
   U101 : NAND2X1 port map( A => n60, B => bitCount_2_port, Y => n264);
   U102 : NOR2X1 port map( A => n277, B => n46, Y => n272);
   U103 : NAND3X1 port map( A => n40, B => n48, C => n263, Y => 
                           nextState_1_port);
   U104 : AOI21X1 port map( A => n35, B => n59, C => n262, Y => n263);
   U105 : NAND2X1 port map( A => n261, B => n260, Y => n262);
   U106 : OAI22X1 port map( A => n268, B => n274, C => n259, D => n273, Y => 
                           n270);
   U107 : OAI22X1 port map( A => n257, B => n256, C => n267, D => 
                           add_89_aco_B_0_port, Y => n258);
   U108 : OAI21X1 port map( A => n253, B => n252, C => n37, Y => n254);
   U109 : OAI22X1 port map( A => n274, B => n56, C => n280, D => n59, Y => n251
                           );
   U110 : NAND3X1 port map( A => n60, B => n64, C => n66, Y => n250);
   U111 : NAND3X1 port map( A => n249, B => n248, C => n247, Y => n255);
   U112 : NOR2X1 port map( A => n277, B => n39, Y => n247);
   U113 : NOR2X1 port map( A => n261, B => n246, Y => n277);
   U114 : NAND3X1 port map( A => EN, B => n45, C => SYNC, Y => n248);
   U115 : OAI21X1 port map( A => n49, B => n44, C => n268, Y => n249);
   U116 : OAI22X1 port map( A => STRB, B => n245, C => n244, D => n243, Y => 
                           nextState2_1_port);
   U117 : NAND3X1 port map( A => bitCount_5_port, B => n42, C => n61, Y => n243
                           );
   U118 : NAND3X1 port map( A => bitCount_3_port, B => n68, C => n242, Y => 
                           n244);
   U119 : NOR2X1 port map( A => state2_1_port, B => state2_0_port, Y => n242);
   U120 : OAI22X1 port map( A => STRB, B => n241, C => n240, D => n239, Y => 
                           nextState2_0_port);
   U121 : NAND2X1 port map( A => n74, B => n72, Y => n239);
   U122 : AOI21X1 port map( A => N348, B => n275, C => n238, Y => n240);
   U123 : OAI21X1 port map( A => n237, B => n236, C => n235, Y => n238);
   U124 : NAND3X1 port map( A => n35, B => n66, C => n61, Y => n235);
   U125 : NAND3X1 port map( A => n67, B => n68, C => bitCount_5_port, Y => n265
                           );
   U126 : NAND2X1 port map( A => n61, B => bitCount_4_port, Y => n236);
   U127 : NAND3X1 port map( A => n233, B => n64, C => n232, Y => n234);
   U128 : NOR2X1 port map( A => bitCount_1_port, B => bitCount_0_port, Y => 
                           n232);
   U129 : NAND3X1 port map( A => n67, B => n69, C => n46, Y => n237);
   U130 : OAI22X1 port map( A => n32, B => n51, C => n231, D => n230, Y => n196
                           );
   U131 : XOR2X1 port map( A => n51, B => n229, Y => n230);
   U132 : NOR2X1 port map( A => n50, B => n228, Y => n229);
   U133 : OAI21X1 port map( A => n227, B => n50, C => n226, Y => n195);
   U134 : NAND3X1 port map( A => n38, B => n50, C => n54, Y => n226);
   U135 : AOI21X1 port map( A => n38, B => n228, C => n225, Y => n227);
   U136 : NAND2X1 port map( A => genCount_1_port, B => genCount_0_port, Y => 
                           n228);
   U137 : OAI21X1 port map( A => n224, B => n55, C => n223, Y => n194);
   U138 : NAND3X1 port map( A => n38, B => n55, C => genCount_0_port, Y => n223
                           );
   U139 : AOI21X1 port map( A => n38, B => n53, C => n225, Y => n224);
   U140 : OAI22X1 port map( A => n32, B => n53, C => genCount_0_port, D => n231
                           , Y => n193);
   U141 : AOI22X1 port map( A => n256, B => n39, C => n246, D => n42, Y => n231
                           );
   U142 : NAND3X1 port map( A => genCount_2_port, B => genCount_0_port, C => 
                           n222, Y => n246);
   U143 : NOR2X1 port map( A => genCount_3_port, B => genCount_1_port, Y => 
                           n222);
   U144 : NAND3X1 port map( A => genCount_1_port, B => n53, C => n221, Y => 
                           n256);
   U145 : NOR2X1 port map( A => genCount_3_port, B => genCount_2_port, Y => 
                           n221);
   U146 : OAI21X1 port map( A => n34, B => n58, C => n220, Y => n192);
   U147 : NAND2X1 port map( A => N116, B => n219, Y => n220);
   U148 : OAI21X1 port map( A => n34, B => n70, C => n218, Y => n191);
   U149 : NAND2X1 port map( A => N115, B => n219, Y => n218);
   U150 : OAI21X1 port map( A => n34, B => n69, C => n217, Y => n190);
   U151 : NAND2X1 port map( A => N114, B => n219, Y => n217);
   U152 : OAI21X1 port map( A => n34, B => n68, C => n216, Y => n189);
   U153 : NAND2X1 port map( A => N113, B => n219, Y => n216);
   U154 : OAI21X1 port map( A => n34, B => n67, C => n215, Y => n188);
   U155 : NAND2X1 port map( A => N112, B => n219, Y => n215);
   U156 : OAI21X1 port map( A => n34, B => n64, C => n214, Y => n187);
   U157 : NAND2X1 port map( A => N111, B => n219, Y => n214);
   U158 : OAI21X1 port map( A => n34, B => n63, C => n213, Y => n186);
   U159 : NAND2X1 port map( A => N110, B => n219, Y => n213);
   U160 : OAI21X1 port map( A => n34, B => n62, C => n212, Y => n185);
   U161 : NAND2X1 port map( A => N109, B => n219, Y => n212);
   U162 : NAND3X1 port map( A => n253, B => n276, C => n36, Y => n219);
   U163 : NAND2X1 port map( A => n56, B => n275, Y => n276);
   U164 : NAND2X1 port map( A => n273, B => n274, Y => n275);
   U165 : OAI21X1 port map( A => n57, B => n211, C => n268, Y => n259);
   U166 : NAND2X1 port map( A => wordCount_4_port, B => wordCount_3_port, Y => 
                           n211);
   U167 : NOR3X1 port map( A => wordCount_1_port, B => wordCount_2_port, C => 
                           wordCount_0_port, Y => n210);
   U168 : NAND3X1 port map( A => n257, B => n209, C => n208, Y => n278);
   U169 : NAND2X1 port map( A => n207, B => n206, Y => n257);
   U170 : NAND2X1 port map( A => state2_0_port, B => n72, Y => n241);
   U171 : NAND2X1 port map( A => state2_1_port, B => n74, Y => n245);
   U172 : NAND3X1 port map( A => n60, B => n65, C => bitCount_4_port, Y => n252
                           );
   U173 : NAND3X1 port map( A => n65, B => n68, C => n60, Y => n268);
   U174 : NAND3X1 port map( A => bitCount_1_port, B => bitCount_0_port, C => 
                           n233, Y => n205);
   U175 : NOR2X1 port map( A => bitCount_7_port, B => bitCount_6_port, Y => 
                           n233);
   U176 : NAND3X1 port map( A => bitCount_2_port, B => n69, C => 
                           bitCount_3_port, Y => n204_port);
   U177 : NAND2X1 port map( A => RST, B => EN, Y => N356);
   U178 : NAND3X1 port map( A => n260, B => n267, C => n203_port, Y => N307);
   U179 : NOR2X1 port map( A => n45, B => n42, Y => n203_port);
   U180 : NAND3X1 port map( A => n273, B => n261, C => n202_port, Y => N306);
   U181 : NOR2X1 port map( A => n46, B => n33, Y => n202_port);
   U182 : NAND2X1 port map( A => n32, B => n261, Y => N304);
   U183 : NAND3X1 port map( A => state_1_port, B => n43, C => n207, Y => n261);
   U184 : NAND3X1 port map( A => n273, B => n208, C => n201_port, Y => n225);
   U185 : NOR2X1 port map( A => n33, B => n200, Y => n201_port);
   U186 : NAND2X1 port map( A => n36, B => n274, Y => N305);
   U187 : NAND3X1 port map( A => n199, B => n52, C => state_3_port, Y => n274);
   U188 : NAND3X1 port map( A => n280, B => n267, C => n260, Y => n198);
   U189 : NAND3X1 port map( A => n197, B => n43, C => state_1_port, Y => n260);
   U190 : NAND3X1 port map( A => state_1_port, B => state_0_port, C => n207, Y 
                           => n267);
   U191 : NAND2X1 port map( A => n206, B => n197, Y => n280);
   U192 : NAND2X1 port map( A => n197, B => n199, Y => n253);
   U193 : NAND3X1 port map( A => state_3_port, B => n52, C => n206, Y => n209);
   U194 : NOR2X1 port map( A => n43, B => state_1_port, Y => n206);
   U195 : NAND2X1 port map( A => n207, B => n199, Y => n208);
   U196 : NOR2X1 port map( A => state_0_port, B => state_1_port, Y => n199);
   U197 : NOR2X1 port map( A => state_2_port, B => state_3_port, Y => n207);
   U198 : NAND3X1 port map( A => state_0_port, B => n197, C => state_1_port, Y 
                           => n273);
   U199 : NOR2X1 port map( A => n52, B => state_3_port, Y => n197);
   r95 : InBlock_0_DW01_inc_1 port map( A(7) => bitCount_7_port, A(6) => 
                           bitCount_6_port, A(5) => bitCount_5_port, A(4) => 
                           bitCount_4_port, A(3) => bitCount_3_port, A(2) => 
                           bitCount_2_port, A(1) => bitCount_1_port, A(0) => 
                           bitCount_0_port, SUM(7) => N116, SUM(6) => N115, 
                           SUM(5) => N114, SUM(4) => N113, SUM(3) => N112, 
                           SUM(2) => N111, SUM(1) => N110, SUM(0) => N109);
   r98_U1_1_1 : HAX1 port map( A => wordCount_1_port, B => wordCount_0_port, YC
                           => r98_carry_2_port, YS => N201);
   r98_U1_1_2 : HAX1 port map( A => wordCount_2_port, B => r98_carry_2_port, YC
                           => r98_carry_3_port, YS => N202);
   r98_U1_1_3 : HAX1 port map( A => wordCount_3_port, B => r98_carry_3_port, YC
                           => r98_carry_4_port, YS => N203);
   U11 : INVX4 port map( A => N356, Y => n75);
   U12 : INVX2 port map( A => n253, Y => n46);
   U13 : INVX2 port map( A => wordCount_0_port, Y => n1);
   U28 : XOR2X1 port map( A => wordCount_4_port, B => add_89_aco_carry_4_port, 
                           Y => N134);
   U33 : AND2X1 port map( A => wordCount_3_port, B => add_89_aco_carry_3_port, 
                           Y => add_89_aco_carry_4_port);
   U34 : XOR2X1 port map( A => add_89_aco_carry_3_port, B => wordCount_3_port, 
                           Y => N133);
   U35 : AND2X1 port map( A => wordCount_2_port, B => add_89_aco_carry_2_port, 
                           Y => add_89_aco_carry_3_port);
   U36 : XOR2X1 port map( A => add_89_aco_carry_2_port, B => wordCount_2_port, 
                           Y => N132);
   U37 : AND2X1 port map( A => wordCount_1_port, B => add_89_aco_carry_1_port, 
                           Y => add_89_aco_carry_2_port);
   U38 : XOR2X1 port map( A => add_89_aco_carry_1_port, B => wordCount_1_port, 
                           Y => N131);
   U39 : XOR2X1 port map( A => wordCount_4_port, B => add_100_aco_carry_4_port,
                           Y => N158);
   U40 : AND2X1 port map( A => wordCount_3_port, B => add_100_aco_carry_3_port,
                           Y => add_100_aco_carry_4_port);
   U41 : XOR2X1 port map( A => add_100_aco_carry_3_port, B => wordCount_3_port,
                           Y => N157);
   U42 : AND2X1 port map( A => wordCount_2_port, B => add_100_aco_carry_2_port,
                           Y => add_100_aco_carry_3_port);
   U43 : XOR2X1 port map( A => add_100_aco_carry_2_port, B => wordCount_2_port,
                           Y => N156);
   U44 : AND2X1 port map( A => wordCount_1_port, B => add_100_aco_carry_1_port,
                           Y => add_100_aco_carry_2_port);
   U45 : XOR2X1 port map( A => add_100_aco_carry_1_port, B => wordCount_1_port,
                           Y => N155);
   U46 : AND2X1 port map( A => wordCount_0_port, B => add_89_aco_B_0_port, Y =>
                           add_89_aco_carry_1_port);
   U47 : XOR2X1 port map( A => add_89_aco_B_0_port, B => wordCount_0_port, Y =>
                           N130);
   U48 : AND2X1 port map( A => wordCount_0_port, B => add_100_aco_B_0_port, Y 
                           => add_100_aco_carry_1_port);
   U49 : XOR2X1 port map( A => add_100_aco_B_0_port, B => wordCount_0_port, Y 
                           => N154);
   U50 : XOR2X1 port map( A => r98_carry_4_port, B => wordCount_4_port, Y => 
                           N204);
   U51 : XOR2X1 port map( A => nextWordCount_0_port, B => wordCount_0_port, Y 
                           => n3);
   U52 : XOR2X1 port map( A => nextWordCount_1_port, B => wordCount_1_port, Y 
                           => n2);
   U53 : NOR2X1 port map( A => n3, B => n2, Y => n31);
   U54 : XNOR2X1 port map( A => nextWordCount_2_port, B => wordCount_2_port, Y 
                           => n29);
   U55 : XOR2X1 port map( A => nextWordCount_3_port, B => wordCount_3_port, Y 
                           => n5);
   U56 : XOR2X1 port map( A => nextWordCount_4_port, B => wordCount_4_port, Y 
                           => n4);
   U57 : NOR2X1 port map( A => n5, B => n4, Y => n6);
   U58 : NAND3X1 port map( A => n31, B => n29, C => n6, Y => N348);
   U59 : INVX2 port map( A => n225, Y => n32);
   U60 : INVX2 port map( A => n209, Y => n33);
   U61 : INVX2 port map( A => n278, Y => n34);
   U62 : INVX2 port map( A => n280, Y => n35);
   U63 : INVX2 port map( A => n198, Y => n36);
   U64 : INVX2 port map( A => n251, Y => n37);
   U65 : INVX2 port map( A => n231, Y => n38);
   U66 : INVX2 port map( A => n257, Y => n39);
   U67 : INVX2 port map( A => n258, Y => n40);
   U68 : INVX2 port map( A => n260, Y => n41);
   U69 : INVX2 port map( A => n261, Y => n42);
   U70 : INVX2 port map( A => state_0_port, Y => n43);
   U71 : INVX2 port map( A => n267, Y => n44);
   U72 : INVX2 port map( A => n208, Y => n45);
   U73 : INVX2 port map( A => n276, Y => n47);
   U74 : INVX2 port map( A => n270, Y => n48);
   U75 : INVX2 port map( A => n273, Y => n49);
   U76 : INVX2 port map( A => genCount_2_port, Y => n50);
   U77 : INVX2 port map( A => genCount_3_port, Y => n51);
   U200 : INVX2 port map( A => state_2_port, Y => n52);
   U201 : INVX2 port map( A => genCount_0_port, Y => n53);
   U202 : INVX2 port map( A => n228, Y => n54);
   U203 : INVX2 port map( A => genCount_1_port, Y => n55);
   U204 : INVX2 port map( A => n259, Y => n56);
   U205 : INVX2 port map( A => n210, Y => n57);
   U206 : INVX2 port map( A => bitCount_7_port, Y => n58);
   U207 : INVX2 port map( A => n268, Y => add_89_aco_B_0_port);
   U208 : INVX2 port map( A => n252, Y => add_100_aco_B_0_port);
   U209 : INVX2 port map( A => n250, Y => n59);
   U210 : INVX2 port map( A => n205, Y => n60);
   U211 : INVX2 port map( A => n234, Y => n61);
   U212 : INVX2 port map( A => bitCount_0_port, Y => n62);
   U213 : INVX2 port map( A => bitCount_1_port, Y => n63);
   U214 : INVX2 port map( A => bitCount_2_port, Y => n64);
   U215 : INVX2 port map( A => n204_port, Y => n65);
   U216 : INVX2 port map( A => n265, Y => n66);
   U217 : INVX2 port map( A => bitCount_3_port, Y => n67);
   U218 : INVX2 port map( A => bitCount_4_port, Y => n68);
   U219 : INVX2 port map( A => bitCount_5_port, Y => n69);
   U220 : INVX2 port map( A => bitCount_6_port, Y => n70);
   U221 : INVX2 port map( A => n241, Y => DataReadyW);
   U222 : INVX2 port map( A => state2_1_port, Y => n72);
   U223 : INVX2 port map( A => n245, Y => DataReadyB);
   U224 : INVX2 port map( A => state2_0_port, Y => n74);

end SYN_A_InBlock;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity SET_N_SHIFT_16_1 is

   port( CLK, RST_N, SHIFT_ENABLE, SET_ENABLE : in std_logic;  DATA_IN : in 
         std_logic_vector (15 downto 0);  SHIFT_OUT : out std_logic);

end SET_N_SHIFT_16_1;

architecture SYN_simple_set_n_shift_reg of SET_N_SHIFT_16_1 is

   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component AND2X2
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component OR2X2
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI21X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component AOI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component DFFSR
      port( D, CLK, R, S : in std_logic;  Q : out std_logic);
   end component;
   
   signal present_val_15_port, present_val_14_port, present_val_13_port, 
      present_val_12_port, present_val_11_port, present_val_10_port, 
      present_val_9_port, present_val_8_port, present_val_7_port, 
      present_val_6_port, present_val_5_port, present_val_4_port, 
      present_val_3_port, present_val_2_port, present_val_1_port, 
      present_val_0_port, next_so, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11
      , n12, n13, n14, n15, n16, n17, n36, n38, n39, n40, n41, n42, n43, n44, 
      n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59
      , n60, n61, n62, n63, n64, n65, n66, n67, n68, n18, n19, n20, n21, n22, 
      n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n37, n69
      , n70, n71 : std_logic;

begin
   
   present_val_reg_0_inst : DFFSR port map( D => n68, CLK => CLK, R => n22, S 
                           => n17, Q => present_val_0_port);
   present_val_reg_1_inst : DFFSR port map( D => n67, CLK => CLK, R => n22, S 
                           => n16, Q => present_val_1_port);
   present_val_reg_2_inst : DFFSR port map( D => n66, CLK => CLK, R => n22, S 
                           => n15, Q => present_val_2_port);
   present_val_reg_3_inst : DFFSR port map( D => n65, CLK => CLK, R => n22, S 
                           => n14, Q => present_val_3_port);
   present_val_reg_4_inst : DFFSR port map( D => n64, CLK => CLK, R => n22, S 
                           => n13, Q => present_val_4_port);
   present_val_reg_5_inst : DFFSR port map( D => n63, CLK => CLK, R => n22, S 
                           => n12, Q => present_val_5_port);
   present_val_reg_6_inst : DFFSR port map( D => n62, CLK => CLK, R => n22, S 
                           => n11, Q => present_val_6_port);
   present_val_reg_7_inst : DFFSR port map( D => n61, CLK => CLK, R => n22, S 
                           => n10, Q => present_val_7_port);
   present_val_reg_8_inst : DFFSR port map( D => n60, CLK => CLK, R => n22, S 
                           => n9, Q => present_val_8_port);
   present_val_reg_9_inst : DFFSR port map( D => n59, CLK => CLK, R => n22, S 
                           => n8, Q => present_val_9_port);
   present_val_reg_10_inst : DFFSR port map( D => n58, CLK => CLK, R => n22, S 
                           => n7, Q => present_val_10_port);
   present_val_reg_11_inst : DFFSR port map( D => n57, CLK => CLK, R => n22, S 
                           => n6, Q => present_val_11_port);
   present_val_reg_12_inst : DFFSR port map( D => n56, CLK => CLK, R => n22, S 
                           => n5, Q => present_val_12_port);
   present_val_reg_13_inst : DFFSR port map( D => n55, CLK => CLK, R => n22, S 
                           => n4, Q => present_val_13_port);
   present_val_reg_14_inst : DFFSR port map( D => n54, CLK => CLK, R => n22, S 
                           => n3, Q => present_val_14_port);
   present_val_reg_15_inst : DFFSR port map( D => n53, CLK => CLK, R => n22, S 
                           => n2, Q => present_val_15_port);
   so_reg : DFFSR port map( D => next_so, CLK => CLK, R => n22, S => n1, Q => 
                           SHIFT_OUT);
   n1 <= '1';
   n2 <= '1';
   n3 <= '1';
   n4 <= '1';
   n5 <= '1';
   n6 <= '1';
   n7 <= '1';
   n8 <= '1';
   n9 <= '1';
   n10 <= '1';
   n11 <= '1';
   n12 <= '1';
   n13 <= '1';
   n14 <= '1';
   n15 <= '1';
   n16 <= '1';
   n17 <= '1';
   U39 : OAI22X1 port map( A => n20, B => n70, C => n21, D => n71, Y => next_so
                           );
   U40 : OAI21X1 port map( A => n71, B => n18, C => n36, Y => n53);
   U41 : AOI22X1 port map( A => present_val_14_port, B => n21, C => DATA_IN(15)
                           , D => n19, Y => n36);
   U42 : OAI21X1 port map( A => n70, B => n18, C => n38, Y => n54);
   U43 : AOI22X1 port map( A => present_val_13_port, B => SHIFT_ENABLE, C => 
                           DATA_IN(14), D => n19, Y => n38);
   U44 : OAI21X1 port map( A => n18, B => n69, C => n39, Y => n55);
   U45 : AOI22X1 port map( A => present_val_12_port, B => n21, C => DATA_IN(13)
                           , D => n19, Y => n39);
   U46 : OAI21X1 port map( A => n18, B => n37, C => n40, Y => n56);
   U47 : AOI22X1 port map( A => present_val_11_port, B => SHIFT_ENABLE, C => 
                           DATA_IN(12), D => n19, Y => n40);
   U48 : OAI21X1 port map( A => n18, B => n35, C => n41, Y => n57);
   U49 : AOI22X1 port map( A => present_val_10_port, B => n21, C => DATA_IN(11)
                           , D => n19, Y => n41);
   U50 : OAI21X1 port map( A => n18, B => n34, C => n42, Y => n58);
   U51 : AOI22X1 port map( A => present_val_9_port, B => SHIFT_ENABLE, C => 
                           DATA_IN(10), D => n19, Y => n42);
   U52 : OAI21X1 port map( A => n18, B => n33, C => n43, Y => n59);
   U53 : AOI22X1 port map( A => present_val_8_port, B => n21, C => DATA_IN(9), 
                           D => n19, Y => n43);
   U54 : OAI21X1 port map( A => n18, B => n32, C => n44, Y => n60);
   U55 : AOI22X1 port map( A => present_val_7_port, B => SHIFT_ENABLE, C => 
                           DATA_IN(8), D => n19, Y => n44);
   U56 : OAI21X1 port map( A => n18, B => n31, C => n45, Y => n61);
   U57 : AOI22X1 port map( A => present_val_6_port, B => n21, C => DATA_IN(7), 
                           D => n19, Y => n45);
   U58 : OAI21X1 port map( A => n18, B => n30, C => n46, Y => n62);
   U59 : AOI22X1 port map( A => present_val_5_port, B => SHIFT_ENABLE, C => 
                           DATA_IN(6), D => n19, Y => n46);
   U60 : OAI21X1 port map( A => n18, B => n29, C => n47, Y => n63);
   U61 : AOI22X1 port map( A => present_val_4_port, B => n21, C => DATA_IN(5), 
                           D => n19, Y => n47);
   U62 : OAI21X1 port map( A => n18, B => n28, C => n48, Y => n64);
   U63 : AOI22X1 port map( A => present_val_3_port, B => n21, C => DATA_IN(4), 
                           D => n19, Y => n48);
   U64 : OAI21X1 port map( A => n18, B => n27, C => n49, Y => n65);
   U65 : AOI22X1 port map( A => present_val_2_port, B => n21, C => DATA_IN(3), 
                           D => n19, Y => n49);
   U66 : OAI21X1 port map( A => n18, B => n26, C => n50, Y => n66);
   U67 : AOI22X1 port map( A => present_val_1_port, B => SHIFT_ENABLE, C => 
                           DATA_IN(2), D => n19, Y => n50);
   U68 : OAI21X1 port map( A => n18, B => n25, C => n51, Y => n67);
   U69 : AOI22X1 port map( A => present_val_0_port, B => n21, C => DATA_IN(1), 
                           D => n19, Y => n51);
   U70 : OAI21X1 port map( A => n18, B => n24, C => n52, Y => n68);
   U71 : NAND2X1 port map( A => DATA_IN(0), B => n19, Y => n52);
   U20 : OR2X2 port map( A => SET_ENABLE, B => n21, Y => n18);
   U21 : AND2X2 port map( A => n18, B => n20, Y => n19);
   U22 : INVX2 port map( A => n23, Y => n22);
   U23 : INVX2 port map( A => n20, Y => n21);
   U24 : INVX2 port map( A => SHIFT_ENABLE, Y => n20);
   U25 : INVX2 port map( A => RST_N, Y => n23);
   U26 : INVX2 port map( A => present_val_0_port, Y => n24);
   U27 : INVX2 port map( A => present_val_1_port, Y => n25);
   U28 : INVX2 port map( A => present_val_2_port, Y => n26);
   U29 : INVX2 port map( A => present_val_3_port, Y => n27);
   U30 : INVX2 port map( A => present_val_4_port, Y => n28);
   U31 : INVX2 port map( A => present_val_5_port, Y => n29);
   U32 : INVX2 port map( A => present_val_6_port, Y => n30);
   U33 : INVX2 port map( A => present_val_7_port, Y => n31);
   U34 : INVX2 port map( A => present_val_8_port, Y => n32);
   U35 : INVX2 port map( A => present_val_9_port, Y => n33);
   U36 : INVX2 port map( A => present_val_10_port, Y => n34);
   U37 : INVX2 port map( A => present_val_11_port, Y => n35);
   U38 : INVX2 port map( A => present_val_12_port, Y => n37);
   U72 : INVX2 port map( A => present_val_13_port, Y => n69);
   U73 : INVX2 port map( A => present_val_14_port, Y => n70);
   U74 : INVX2 port map( A => present_val_15_port, Y => n71);

end SYN_simple_set_n_shift_reg;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity SHIFT_REG_16_3 is

   port( CLK, RST_N, SHIFT_ENABLE, D_ORIG : in std_logic;  RCV_DATA : out 
         std_logic_vector (15 downto 0));

end SHIFT_REG_16_3;

architecture SYN_simple_shift_reg of SHIFT_REG_16_3 is

   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component BUFX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI21X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component DFFSR
      port( D, CLK, R, S : in std_logic;  Q : out std_logic);
   end component;
   
   signal RCV_DATA_15_port, RCV_DATA_14_port, RCV_DATA_13_port, 
      RCV_DATA_12_port, RCV_DATA_11_port, RCV_DATA_10_port, RCV_DATA_9_port, 
      RCV_DATA_8_port, RCV_DATA_7_port, RCV_DATA_6_port, RCV_DATA_5_port, 
      RCV_DATA_4_port, RCV_DATA_3_port, RCV_DATA_2_port, RCV_DATA_1_port, 
      RCV_DATA_0_port, n3, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, 
      n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42
      , n43, n44, n45, n46, n47, n48, n49, n50, n1, n2, n4, n5, n6, n7, n8, n9,
      n10, n11, n12, n13, n14, n15, n16, n17, n51, n52, n53, n54 : std_logic;

begin
   RCV_DATA <= ( RCV_DATA_15_port, RCV_DATA_14_port, RCV_DATA_13_port, 
      RCV_DATA_12_port, RCV_DATA_11_port, RCV_DATA_10_port, RCV_DATA_9_port, 
      RCV_DATA_8_port, RCV_DATA_7_port, RCV_DATA_6_port, RCV_DATA_5_port, 
      RCV_DATA_4_port, RCV_DATA_3_port, RCV_DATA_2_port, RCV_DATA_1_port, 
      RCV_DATA_0_port );
   
   present_val_reg_0_inst : DFFSR port map( D => n50, CLK => CLK, R => RST_N, S
                           => n49, Q => RCV_DATA_0_port);
   present_val_reg_1_inst : DFFSR port map( D => n48, CLK => CLK, R => RST_N, S
                           => n47, Q => RCV_DATA_1_port);
   present_val_reg_2_inst : DFFSR port map( D => n46, CLK => CLK, R => RST_N, S
                           => n45, Q => RCV_DATA_2_port);
   present_val_reg_3_inst : DFFSR port map( D => n44, CLK => CLK, R => RST_N, S
                           => n43, Q => RCV_DATA_3_port);
   present_val_reg_4_inst : DFFSR port map( D => n42, CLK => CLK, R => RST_N, S
                           => n41, Q => RCV_DATA_4_port);
   present_val_reg_5_inst : DFFSR port map( D => n40, CLK => CLK, R => RST_N, S
                           => n39, Q => RCV_DATA_5_port);
   present_val_reg_6_inst : DFFSR port map( D => n38, CLK => CLK, R => RST_N, S
                           => n37, Q => RCV_DATA_6_port);
   present_val_reg_7_inst : DFFSR port map( D => n36, CLK => CLK, R => RST_N, S
                           => n35, Q => RCV_DATA_7_port);
   present_val_reg_8_inst : DFFSR port map( D => n34, CLK => CLK, R => RST_N, S
                           => n33, Q => RCV_DATA_8_port);
   present_val_reg_9_inst : DFFSR port map( D => n32, CLK => CLK, R => RST_N, S
                           => n31, Q => RCV_DATA_9_port);
   present_val_reg_10_inst : DFFSR port map( D => n30, CLK => CLK, R => RST_N, 
                           S => n29, Q => RCV_DATA_10_port);
   present_val_reg_11_inst : DFFSR port map( D => n28, CLK => CLK, R => RST_N, 
                           S => n27, Q => RCV_DATA_11_port);
   present_val_reg_12_inst : DFFSR port map( D => n26, CLK => CLK, R => RST_N, 
                           S => n25, Q => RCV_DATA_12_port);
   present_val_reg_13_inst : DFFSR port map( D => n24, CLK => CLK, R => RST_N, 
                           S => n23, Q => RCV_DATA_13_port);
   present_val_reg_14_inst : DFFSR port map( D => n22, CLK => CLK, R => RST_N, 
                           S => n21, Q => RCV_DATA_14_port);
   present_val_reg_15_inst : DFFSR port map( D => n20, CLK => CLK, R => RST_N, 
                           S => n19, Q => RCV_DATA_15_port);
   U2 : OAI21X1 port map( A => n54, B => n6, C => n3, Y => n20);
   U3 : NAND2X1 port map( A => RCV_DATA_15_port, B => n6, Y => n3);
   U4 : OAI22X1 port map( A => n1, B => n54, C => n6, D => n53, Y => n22);
   U6 : OAI22X1 port map( A => n1, B => n53, C => n6, D => n52, Y => n24);
   U8 : OAI22X1 port map( A => n4, B => n52, C => n6, D => n51, Y => n26);
   U10 : OAI22X1 port map( A => n2, B => n51, C => n6, D => n17, Y => n28);
   U12 : OAI22X1 port map( A => n6, B => n16, C => n1, D => n17, Y => n30);
   U14 : OAI22X1 port map( A => n2, B => n16, C => n6, D => n15, Y => n32);
   U16 : OAI22X1 port map( A => n2, B => n15, C => n6, D => n14, Y => n34);
   U18 : OAI22X1 port map( A => n4, B => n14, C => n6, D => n13, Y => n36);
   U20 : OAI22X1 port map( A => n4, B => n13, C => n6, D => n12, Y => n38);
   U22 : OAI22X1 port map( A => n4, B => n12, C => n6, D => n11, Y => n40);
   U24 : OAI22X1 port map( A => n4, B => n11, C => n6, D => n10, Y => n42);
   U26 : OAI22X1 port map( A => n4, B => n10, C => n6, D => n9, Y => n44);
   U28 : OAI22X1 port map( A => n4, B => n9, C => n6, D => n8, Y => n46);
   U30 : OAI22X1 port map( A => n5, B => n8, C => n6, D => n7, Y => n48);
   U33 : OAI21X1 port map( A => n5, B => n7, C => n18, Y => n50);
   U34 : NAND2X1 port map( A => D_ORIG, B => n1, Y => n18);
   n19 <= '1';
   n21 <= '1';
   n23 <= '1';
   n25 <= '1';
   n27 <= '1';
   n29 <= '1';
   n31 <= '1';
   n33 <= '1';
   n35 <= '1';
   n37 <= '1';
   n39 <= '1';
   n41 <= '1';
   n43 <= '1';
   n45 <= '1';
   n47 <= '1';
   n49 <= '1';
   U5 : INVX2 port map( A => n1, Y => n6);
   U7 : BUFX2 port map( A => SHIFT_ENABLE, Y => n1);
   U9 : BUFX2 port map( A => SHIFT_ENABLE, Y => n2);
   U11 : BUFX2 port map( A => SHIFT_ENABLE, Y => n4);
   U13 : BUFX2 port map( A => SHIFT_ENABLE, Y => n5);
   U15 : INVX2 port map( A => RCV_DATA_0_port, Y => n7);
   U17 : INVX2 port map( A => RCV_DATA_1_port, Y => n8);
   U19 : INVX2 port map( A => RCV_DATA_2_port, Y => n9);
   U21 : INVX2 port map( A => RCV_DATA_3_port, Y => n10);
   U23 : INVX2 port map( A => RCV_DATA_4_port, Y => n11);
   U25 : INVX2 port map( A => RCV_DATA_5_port, Y => n12);
   U27 : INVX2 port map( A => RCV_DATA_6_port, Y => n13);
   U29 : INVX2 port map( A => RCV_DATA_7_port, Y => n14);
   U31 : INVX2 port map( A => RCV_DATA_8_port, Y => n15);
   U32 : INVX2 port map( A => RCV_DATA_9_port, Y => n16);
   U35 : INVX2 port map( A => RCV_DATA_10_port, Y => n17);
   U52 : INVX2 port map( A => RCV_DATA_11_port, Y => n51);
   U53 : INVX2 port map( A => RCV_DATA_12_port, Y => n52);
   U54 : INVX2 port map( A => RCV_DATA_13_port, Y => n53);
   U55 : INVX2 port map( A => RCV_DATA_14_port, Y => n54);

end SYN_simple_shift_reg;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity InBlock_1 is

   port( RST, BCLK, EN, SYNC, STRB : in std_logic;  DataReadyB, DataReadyW, 
         Shift1En, Shift2En, ZeroPad : out std_logic);

end InBlock_1;

architecture SYN_A_InBlock of InBlock_1 is

   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND3X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component NOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component XNOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component AND2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component INVX4
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component HAX1
      port( A, B : in std_logic;  YC, YS : out std_logic);
   end component;
   
   component InBlock_1_DW01_inc_1
      port( A : in std_logic_vector (7 downto 0);  SUM : out std_logic_vector 
            (7 downto 0));
   end component;
   
   component NAND2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component NOR3X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI21X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component AOI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component AOI21X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component OR2X2
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component AND2X2
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component LATCH
      port( CLK, D : in std_logic;  Q : out std_logic);
   end component;
   
   component DFFSR
      port( D, CLK, R, S : in std_logic;  Q : out std_logic);
   end component;
   
   signal bitCount_7_port, bitCount_6_port, bitCount_5_port, bitCount_4_port, 
      bitCount_3_port, bitCount_2_port, bitCount_1_port, bitCount_0_port, 
      wordCount_4_port, wordCount_3_port, wordCount_2_port, wordCount_1_port, 
      wordCount_0_port, genCount_3_port, genCount_2_port, genCount_1_port, 
      genCount_0_port, state_3_port, state_2_port, state_1_port, state_0_port, 
      state2_1_port, state2_0_port, nextState_3_port, nextState_2_port, 
      nextState_1_port, nextState_0_port, nextState2_1_port, nextState2_0_port,
      nextWordCount_4_port, nextWordCount_3_port, nextWordCount_2_port, 
      nextWordCount_1_port, nextWordCount_0_port, N109, N110, N111, N112, N113,
      N114, N115, N116, N130, N131, N132, N133, N134, N154, N155, N156, N157, 
      N158, N201, N202, N203, N204, N304, N305, N306, N307, N348, N356, n7, n8,
      n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23,
      n24, n25, n26, n27, n28, n30, n76, n77, n78, n79, n80, n81, n82, n83, n84
      , n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, 
      n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109_port, 
      n110_port, n111_port, n112_port, n113_port, n114_port, n115_port, 
      n116_port, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, 
      n127, n128, n129, n130_port, n131_port, n132_port, n133_port, n134_port, 
      n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, 
      n147, n148, n149, n150, n151, n152, n153, n154_port, n155_port, n156_port
      , n157_port, n158_port, n159, n160, n161, n162, n163, n164, n165, n166, 
      n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, 
      n179, n180, n181, n182, n183, n184, add_100_aco_carry_1_port, 
      add_100_aco_carry_2_port, add_100_aco_carry_3_port, 
      add_100_aco_carry_4_port, add_100_aco_B_0_port, add_89_aco_carry_1_port, 
      add_89_aco_carry_2_port, add_89_aco_carry_3_port, add_89_aco_carry_4_port
      , add_89_aco_B_0_port, r98_carry_2_port, r98_carry_3_port, 
      r98_carry_4_port, n1, n2, n3, n4, n5, n6, n29, n31, n32, n33, n34, n35, 
      n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50
      , n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, 
      n65, n66, n67, n68, n69, n70, n72, n74, n75 : std_logic;

begin
   
   state_reg_0_inst : DFFSR port map( D => nextState_0_port, CLK => BCLK, R => 
                           n75, S => n30, Q => state_0_port);
   genCount_reg_2_inst : DFFSR port map( D => n174, CLK => BCLK, R => n75, S =>
                           n28, Q => genCount_2_port);
   genCount_reg_3_inst : DFFSR port map( D => n173, CLK => BCLK, R => n75, S =>
                           n27, Q => genCount_3_port);
   state_reg_2_inst : DFFSR port map( D => nextState_2_port, CLK => BCLK, R => 
                           n75, S => n26, Q => state_2_port);
   genCount_reg_0_inst : DFFSR port map( D => n176, CLK => BCLK, R => n75, S =>
                           n25, Q => genCount_0_port);
   genCount_reg_1_inst : DFFSR port map( D => n175, CLK => BCLK, R => n75, S =>
                           n24, Q => genCount_1_port);
   state_reg_1_inst : DFFSR port map( D => nextState_1_port, CLK => BCLK, R => 
                           n75, S => n23, Q => state_1_port);
   wordCount_reg_0_inst : DFFSR port map( D => nextWordCount_0_port, CLK => 
                           BCLK, R => n75, S => n22, Q => wordCount_0_port);
   state_reg_3_inst : DFFSR port map( D => nextState_3_port, CLK => BCLK, R => 
                           n75, S => n21, Q => state_3_port);
   bitCount_reg_7_inst : DFFSR port map( D => n177, CLK => BCLK, R => n75, S =>
                           n20, Q => bitCount_7_port);
   bitCount_reg_0_inst : DFFSR port map( D => n184, CLK => BCLK, R => n75, S =>
                           n19, Q => bitCount_0_port);
   bitCount_reg_1_inst : DFFSR port map( D => n183, CLK => BCLK, R => n75, S =>
                           n18, Q => bitCount_1_port);
   bitCount_reg_2_inst : DFFSR port map( D => n182, CLK => BCLK, R => n75, S =>
                           n17, Q => bitCount_2_port);
   bitCount_reg_3_inst : DFFSR port map( D => n181, CLK => BCLK, R => n75, S =>
                           n16, Q => bitCount_3_port);
   bitCount_reg_4_inst : DFFSR port map( D => n180, CLK => BCLK, R => n75, S =>
                           n15, Q => bitCount_4_port);
   bitCount_reg_5_inst : DFFSR port map( D => n179, CLK => BCLK, R => n75, S =>
                           n14, Q => bitCount_5_port);
   bitCount_reg_6_inst : DFFSR port map( D => n178, CLK => BCLK, R => n75, S =>
                           n13, Q => bitCount_6_port);
   wordCount_reg_4_inst : DFFSR port map( D => nextWordCount_4_port, CLK => 
                           BCLK, R => n75, S => n12, Q => wordCount_4_port);
   wordCount_reg_3_inst : DFFSR port map( D => nextWordCount_3_port, CLK => 
                           BCLK, R => n75, S => n11, Q => wordCount_3_port);
   wordCount_reg_1_inst : DFFSR port map( D => nextWordCount_1_port, CLK => 
                           BCLK, R => n75, S => n10, Q => wordCount_1_port);
   wordCount_reg_2_inst : DFFSR port map( D => nextWordCount_2_port, CLK => 
                           BCLK, R => n75, S => n9, Q => wordCount_2_port);
   state2_reg_1_inst : DFFSR port map( D => nextState2_1_port, CLK => BCLK, R 
                           => n75, S => n8, Q => state2_1_port);
   state2_reg_0_inst : DFFSR port map( D => nextState2_0_port, CLK => BCLK, R 
                           => n75, S => n7, Q => state2_0_port);
   ZeroPad_reg : LATCH port map( CLK => N307, D => n41, Q => ZeroPad);
   Shift1En_reg : LATCH port map( CLK => N304, D => N305, Q => Shift1En);
   Shift2En_reg : LATCH port map( CLK => N304, D => N306, Q => Shift2En);
   n7 <= '1';
   n8 <= '1';
   n9 <= '1';
   n10 <= '1';
   n11 <= '1';
   n12 <= '1';
   n13 <= '1';
   n14 <= '1';
   n15 <= '1';
   n16 <= '1';
   n17 <= '1';
   n18 <= '1';
   n19 <= '1';
   n20 <= '1';
   n21 <= '1';
   n22 <= '1';
   n23 <= '1';
   n24 <= '1';
   n25 <= '1';
   n26 <= '1';
   n27 <= '1';
   n28 <= '1';
   n30 <= '1';
   U30 : AND2X2 port map( A => add_89_aco_B_0_port, B => n94, Y => n78);
   U31 : OR2X2 port map( A => n114_port, B => n115_port, Y => nextState_0_port)
                           ;
   U32 : OR2X2 port map( A => n46, B => N305, Y => n169);
   U78 : NAND2X1 port map( A => n76, B => n77, Y => nextWordCount_4_port);
   U79 : AOI22X1 port map( A => N204, B => n78, C => wordCount_4_port, D => n79
                           , Y => n77);
   U80 : AOI22X1 port map( A => N158, B => n46, C => N134, D => n44, Y => n76);
   U81 : NAND2X1 port map( A => n80, B => n81, Y => nextWordCount_3_port);
   U82 : AOI22X1 port map( A => N203, B => n78, C => wordCount_3_port, D => n79
                           , Y => n81);
   U83 : AOI22X1 port map( A => N157, B => n46, C => N133, D => n44, Y => n80);
   U84 : NAND2X1 port map( A => n82, B => n83, Y => nextWordCount_2_port);
   U85 : AOI22X1 port map( A => N202, B => n78, C => wordCount_2_port, D => n79
                           , Y => n83);
   U86 : AOI22X1 port map( A => N156, B => n46, C => N132, D => n44, Y => n82);
   U87 : NAND2X1 port map( A => n84, B => n85, Y => nextWordCount_1_port);
   U88 : AOI22X1 port map( A => N201, B => n78, C => wordCount_1_port, D => n79
                           , Y => n85);
   U89 : AOI22X1 port map( A => N155, B => n46, C => N131, D => n44, Y => n84);
   U90 : NAND2X1 port map( A => n86, B => n87, Y => nextWordCount_0_port);
   U91 : AOI22X1 port map( A => n1, B => n78, C => wordCount_0_port, D => n79, 
                           Y => n87);
   U92 : NAND3X1 port map( A => n88, B => n89, C => n90, Y => n79);
   U93 : NOR2X1 port map( A => n41, B => n91, Y => n90);
   U94 : NOR2X1 port map( A => n92, B => n47, Y => n88);
   U95 : AOI22X1 port map( A => N154, B => n46, C => N130, D => n44, Y => n86);
   U96 : OAI22X1 port map( A => add_89_aco_B_0_port, B => n95, C => n56, D => 
                           n96, Y => nextState_3_port);
   U97 : NAND3X1 port map( A => n97, B => n89, C => n98, Y => nextState_2_port)
                           ;
   U98 : NOR2X1 port map( A => n99, B => n100, Y => n98);
   U99 : OAI21X1 port map( A => n101, B => n102, C => n103, Y => n100);
   U100 : OAI21X1 port map( A => n104, B => n105, C => n41, Y => n103);
   U101 : NAND2X1 port map( A => n60, B => bitCount_2_port, Y => n105);
   U102 : NOR2X1 port map( A => n92, B => n46, Y => n97);
   U103 : NAND3X1 port map( A => n40, B => n48, C => n106, Y => 
                           nextState_1_port);
   U104 : AOI21X1 port map( A => n35, B => n59, C => n107, Y => n106);
   U105 : NAND2X1 port map( A => n108, B => n109_port, Y => n107);
   U106 : OAI22X1 port map( A => n101, B => n95, C => n110_port, D => n96, Y =>
                           n99);
   U107 : OAI22X1 port map( A => n112_port, B => n113_port, C => n102, D => 
                           add_89_aco_B_0_port, Y => n111_port);
   U108 : OAI21X1 port map( A => n116_port, B => n117, C => n37, Y => n115_port
                           );
   U109 : OAI22X1 port map( A => n95, B => n56, C => n89, D => n59, Y => n118);
   U110 : NAND3X1 port map( A => n60, B => n64, C => n66, Y => n119);
   U111 : NAND3X1 port map( A => n120, B => n121, C => n122, Y => n114_port);
   U112 : NOR2X1 port map( A => n92, B => n39, Y => n122);
   U113 : NOR2X1 port map( A => n108, B => n123, Y => n92);
   U114 : NAND3X1 port map( A => EN, B => n45, C => SYNC, Y => n121);
   U115 : OAI21X1 port map( A => n49, B => n44, C => n101, Y => n120);
   U116 : OAI22X1 port map( A => STRB, B => n124, C => n125, D => n126, Y => 
                           nextState2_1_port);
   U117 : NAND3X1 port map( A => bitCount_5_port, B => n42, C => n61, Y => n126
                           );
   U118 : NAND3X1 port map( A => bitCount_3_port, B => n68, C => n127, Y => 
                           n125);
   U119 : NOR2X1 port map( A => state2_1_port, B => state2_0_port, Y => n127);
   U120 : OAI22X1 port map( A => STRB, B => n128, C => n129, D => n130_port, Y 
                           => nextState2_0_port);
   U121 : NAND2X1 port map( A => n74, B => n72, Y => n130_port);
   U122 : AOI21X1 port map( A => N348, B => n94, C => n131_port, Y => n129);
   U123 : OAI21X1 port map( A => n132_port, B => n133_port, C => n134_port, Y 
                           => n131_port);
   U124 : NAND3X1 port map( A => n35, B => n66, C => n61, Y => n134_port);
   U125 : NAND3X1 port map( A => n67, B => n68, C => bitCount_5_port, Y => n104
                           );
   U126 : NAND2X1 port map( A => n61, B => bitCount_4_port, Y => n133_port);
   U127 : NAND3X1 port map( A => n136, B => n64, C => n137, Y => n135);
   U128 : NOR2X1 port map( A => bitCount_1_port, B => bitCount_0_port, Y => 
                           n137);
   U129 : NAND3X1 port map( A => n67, B => n69, C => n46, Y => n132_port);
   U130 : OAI22X1 port map( A => n32, B => n51, C => n138, D => n139, Y => n173
                           );
   U131 : XOR2X1 port map( A => n51, B => n140, Y => n139);
   U132 : NOR2X1 port map( A => n50, B => n141, Y => n140);
   U133 : OAI21X1 port map( A => n142, B => n50, C => n143, Y => n174);
   U134 : NAND3X1 port map( A => n38, B => n50, C => n54, Y => n143);
   U135 : AOI21X1 port map( A => n38, B => n141, C => n144, Y => n142);
   U136 : NAND2X1 port map( A => genCount_1_port, B => genCount_0_port, Y => 
                           n141);
   U137 : OAI21X1 port map( A => n145, B => n55, C => n146, Y => n175);
   U138 : NAND3X1 port map( A => n38, B => n55, C => genCount_0_port, Y => n146
                           );
   U139 : AOI21X1 port map( A => n38, B => n53, C => n144, Y => n145);
   U140 : OAI22X1 port map( A => n32, B => n53, C => genCount_0_port, D => n138
                           , Y => n176);
   U141 : AOI22X1 port map( A => n113_port, B => n39, C => n123, D => n42, Y =>
                           n138);
   U142 : NAND3X1 port map( A => genCount_2_port, B => genCount_0_port, C => 
                           n147, Y => n123);
   U143 : NOR2X1 port map( A => genCount_3_port, B => genCount_1_port, Y => 
                           n147);
   U144 : NAND3X1 port map( A => genCount_1_port, B => n53, C => n148, Y => 
                           n113_port);
   U145 : NOR2X1 port map( A => genCount_3_port, B => genCount_2_port, Y => 
                           n148);
   U146 : OAI21X1 port map( A => n34, B => n58, C => n149, Y => n177);
   U147 : NAND2X1 port map( A => N116, B => n150, Y => n149);
   U148 : OAI21X1 port map( A => n34, B => n70, C => n151, Y => n178);
   U149 : NAND2X1 port map( A => N115, B => n150, Y => n151);
   U150 : OAI21X1 port map( A => n34, B => n69, C => n152, Y => n179);
   U151 : NAND2X1 port map( A => N114, B => n150, Y => n152);
   U152 : OAI21X1 port map( A => n34, B => n68, C => n153, Y => n180);
   U153 : NAND2X1 port map( A => N113, B => n150, Y => n153);
   U154 : OAI21X1 port map( A => n34, B => n67, C => n154_port, Y => n181);
   U155 : NAND2X1 port map( A => N112, B => n150, Y => n154_port);
   U156 : OAI21X1 port map( A => n34, B => n64, C => n155_port, Y => n182);
   U157 : NAND2X1 port map( A => N111, B => n150, Y => n155_port);
   U158 : OAI21X1 port map( A => n34, B => n63, C => n156_port, Y => n183);
   U159 : NAND2X1 port map( A => N110, B => n150, Y => n156_port);
   U160 : OAI21X1 port map( A => n34, B => n62, C => n157_port, Y => n184);
   U161 : NAND2X1 port map( A => N109, B => n150, Y => n157_port);
   U162 : NAND3X1 port map( A => n116_port, B => n93, C => n36, Y => n150);
   U163 : NAND2X1 port map( A => n56, B => n94, Y => n93);
   U164 : NAND2X1 port map( A => n96, B => n95, Y => n94);
   U165 : OAI21X1 port map( A => n57, B => n158_port, C => n101, Y => n110_port
                           );
   U166 : NAND2X1 port map( A => wordCount_4_port, B => wordCount_3_port, Y => 
                           n158_port);
   U167 : NOR3X1 port map( A => wordCount_1_port, B => wordCount_2_port, C => 
                           wordCount_0_port, Y => n159);
   U168 : NAND3X1 port map( A => n112_port, B => n160, C => n161, Y => n91);
   U169 : NAND2X1 port map( A => n162, B => n163, Y => n112_port);
   U170 : NAND2X1 port map( A => state2_0_port, B => n72, Y => n128);
   U171 : NAND2X1 port map( A => state2_1_port, B => n74, Y => n124);
   U172 : NAND3X1 port map( A => n60, B => n65, C => bitCount_4_port, Y => n117
                           );
   U173 : NAND3X1 port map( A => n65, B => n68, C => n60, Y => n101);
   U174 : NAND3X1 port map( A => bitCount_1_port, B => bitCount_0_port, C => 
                           n136, Y => n164);
   U175 : NOR2X1 port map( A => bitCount_7_port, B => bitCount_6_port, Y => 
                           n136);
   U176 : NAND3X1 port map( A => bitCount_2_port, B => n69, C => 
                           bitCount_3_port, Y => n165);
   U177 : NAND2X1 port map( A => RST, B => EN, Y => N356);
   U178 : NAND3X1 port map( A => n109_port, B => n102, C => n166, Y => N307);
   U179 : NOR2X1 port map( A => n45, B => n42, Y => n166);
   U180 : NAND3X1 port map( A => n96, B => n108, C => n167, Y => N306);
   U181 : NOR2X1 port map( A => n46, B => n33, Y => n167);
   U182 : NAND2X1 port map( A => n32, B => n108, Y => N304);
   U183 : NAND3X1 port map( A => state_1_port, B => n43, C => n162, Y => n108);
   U184 : NAND3X1 port map( A => n96, B => n161, C => n168, Y => n144);
   U185 : NOR2X1 port map( A => n33, B => n169, Y => n168);
   U186 : NAND2X1 port map( A => n36, B => n95, Y => N305);
   U187 : NAND3X1 port map( A => n170, B => n52, C => state_3_port, Y => n95);
   U188 : NAND3X1 port map( A => n89, B => n102, C => n109_port, Y => n171);
   U189 : NAND3X1 port map( A => n172, B => n43, C => state_1_port, Y => 
                           n109_port);
   U190 : NAND3X1 port map( A => state_1_port, B => state_0_port, C => n162, Y 
                           => n102);
   U191 : NAND2X1 port map( A => n163, B => n172, Y => n89);
   U192 : NAND2X1 port map( A => n172, B => n170, Y => n116_port);
   U193 : NAND3X1 port map( A => state_3_port, B => n52, C => n163, Y => n160);
   U194 : NOR2X1 port map( A => n43, B => state_1_port, Y => n163);
   U195 : NAND2X1 port map( A => n162, B => n170, Y => n161);
   U196 : NOR2X1 port map( A => state_0_port, B => state_1_port, Y => n170);
   U197 : NOR2X1 port map( A => state_2_port, B => state_3_port, Y => n162);
   U198 : NAND3X1 port map( A => state_0_port, B => n172, C => state_1_port, Y 
                           => n96);
   U199 : NOR2X1 port map( A => n52, B => state_3_port, Y => n172);
   r95 : InBlock_1_DW01_inc_1 port map( A(7) => bitCount_7_port, A(6) => 
                           bitCount_6_port, A(5) => bitCount_5_port, A(4) => 
                           bitCount_4_port, A(3) => bitCount_3_port, A(2) => 
                           bitCount_2_port, A(1) => bitCount_1_port, A(0) => 
                           bitCount_0_port, SUM(7) => N116, SUM(6) => N115, 
                           SUM(5) => N114, SUM(4) => N113, SUM(3) => N112, 
                           SUM(2) => N111, SUM(1) => N110, SUM(0) => N109);
   r98_U1_1_1 : HAX1 port map( A => wordCount_1_port, B => wordCount_0_port, YC
                           => r98_carry_2_port, YS => N201);
   r98_U1_1_2 : HAX1 port map( A => wordCount_2_port, B => r98_carry_2_port, YC
                           => r98_carry_3_port, YS => N202);
   r98_U1_1_3 : HAX1 port map( A => wordCount_3_port, B => r98_carry_3_port, YC
                           => r98_carry_4_port, YS => N203);
   U11 : INVX4 port map( A => N356, Y => n75);
   U12 : INVX2 port map( A => n116_port, Y => n46);
   U13 : INVX2 port map( A => wordCount_0_port, Y => n1);
   U28 : XOR2X1 port map( A => wordCount_4_port, B => add_89_aco_carry_4_port, 
                           Y => N134);
   U33 : AND2X1 port map( A => wordCount_3_port, B => add_89_aco_carry_3_port, 
                           Y => add_89_aco_carry_4_port);
   U34 : XOR2X1 port map( A => add_89_aco_carry_3_port, B => wordCount_3_port, 
                           Y => N133);
   U35 : AND2X1 port map( A => wordCount_2_port, B => add_89_aco_carry_2_port, 
                           Y => add_89_aco_carry_3_port);
   U36 : XOR2X1 port map( A => add_89_aco_carry_2_port, B => wordCount_2_port, 
                           Y => N132);
   U37 : AND2X1 port map( A => wordCount_1_port, B => add_89_aco_carry_1_port, 
                           Y => add_89_aco_carry_2_port);
   U38 : XOR2X1 port map( A => add_89_aco_carry_1_port, B => wordCount_1_port, 
                           Y => N131);
   U39 : XOR2X1 port map( A => wordCount_4_port, B => add_100_aco_carry_4_port,
                           Y => N158);
   U40 : AND2X1 port map( A => wordCount_3_port, B => add_100_aco_carry_3_port,
                           Y => add_100_aco_carry_4_port);
   U41 : XOR2X1 port map( A => add_100_aco_carry_3_port, B => wordCount_3_port,
                           Y => N157);
   U42 : AND2X1 port map( A => wordCount_2_port, B => add_100_aco_carry_2_port,
                           Y => add_100_aco_carry_3_port);
   U43 : XOR2X1 port map( A => add_100_aco_carry_2_port, B => wordCount_2_port,
                           Y => N156);
   U44 : AND2X1 port map( A => wordCount_1_port, B => add_100_aco_carry_1_port,
                           Y => add_100_aco_carry_2_port);
   U45 : XOR2X1 port map( A => add_100_aco_carry_1_port, B => wordCount_1_port,
                           Y => N155);
   U46 : AND2X1 port map( A => wordCount_0_port, B => add_89_aco_B_0_port, Y =>
                           add_89_aco_carry_1_port);
   U47 : XOR2X1 port map( A => add_89_aco_B_0_port, B => wordCount_0_port, Y =>
                           N130);
   U48 : AND2X1 port map( A => wordCount_0_port, B => add_100_aco_B_0_port, Y 
                           => add_100_aco_carry_1_port);
   U49 : XOR2X1 port map( A => add_100_aco_B_0_port, B => wordCount_0_port, Y 
                           => N154);
   U50 : XOR2X1 port map( A => r98_carry_4_port, B => wordCount_4_port, Y => 
                           N204);
   U51 : XOR2X1 port map( A => nextWordCount_0_port, B => wordCount_0_port, Y 
                           => n3);
   U52 : XOR2X1 port map( A => nextWordCount_1_port, B => wordCount_1_port, Y 
                           => n2);
   U53 : NOR2X1 port map( A => n3, B => n2, Y => n31);
   U54 : XNOR2X1 port map( A => nextWordCount_2_port, B => wordCount_2_port, Y 
                           => n29);
   U55 : XOR2X1 port map( A => nextWordCount_3_port, B => wordCount_3_port, Y 
                           => n5);
   U56 : XOR2X1 port map( A => nextWordCount_4_port, B => wordCount_4_port, Y 
                           => n4);
   U57 : NOR2X1 port map( A => n5, B => n4, Y => n6);
   U58 : NAND3X1 port map( A => n31, B => n29, C => n6, Y => N348);
   U59 : INVX2 port map( A => n144, Y => n32);
   U60 : INVX2 port map( A => n160, Y => n33);
   U61 : INVX2 port map( A => n91, Y => n34);
   U62 : INVX2 port map( A => n89, Y => n35);
   U63 : INVX2 port map( A => n171, Y => n36);
   U64 : INVX2 port map( A => n118, Y => n37);
   U65 : INVX2 port map( A => n138, Y => n38);
   U66 : INVX2 port map( A => n112_port, Y => n39);
   U67 : INVX2 port map( A => n111_port, Y => n40);
   U68 : INVX2 port map( A => n109_port, Y => n41);
   U69 : INVX2 port map( A => n108, Y => n42);
   U70 : INVX2 port map( A => state_0_port, Y => n43);
   U71 : INVX2 port map( A => n102, Y => n44);
   U72 : INVX2 port map( A => n161, Y => n45);
   U73 : INVX2 port map( A => n93, Y => n47);
   U74 : INVX2 port map( A => n99, Y => n48);
   U75 : INVX2 port map( A => n96, Y => n49);
   U76 : INVX2 port map( A => genCount_2_port, Y => n50);
   U77 : INVX2 port map( A => genCount_3_port, Y => n51);
   U200 : INVX2 port map( A => state_2_port, Y => n52);
   U201 : INVX2 port map( A => genCount_0_port, Y => n53);
   U202 : INVX2 port map( A => n141, Y => n54);
   U203 : INVX2 port map( A => genCount_1_port, Y => n55);
   U204 : INVX2 port map( A => n110_port, Y => n56);
   U205 : INVX2 port map( A => n159, Y => n57);
   U206 : INVX2 port map( A => bitCount_7_port, Y => n58);
   U207 : INVX2 port map( A => n101, Y => add_89_aco_B_0_port);
   U208 : INVX2 port map( A => n117, Y => add_100_aco_B_0_port);
   U209 : INVX2 port map( A => n119, Y => n59);
   U210 : INVX2 port map( A => n164, Y => n60);
   U211 : INVX2 port map( A => n135, Y => n61);
   U212 : INVX2 port map( A => bitCount_0_port, Y => n62);
   U213 : INVX2 port map( A => bitCount_1_port, Y => n63);
   U214 : INVX2 port map( A => bitCount_2_port, Y => n64);
   U215 : INVX2 port map( A => n165, Y => n65);
   U216 : INVX2 port map( A => n104, Y => n66);
   U217 : INVX2 port map( A => bitCount_3_port, Y => n67);
   U218 : INVX2 port map( A => bitCount_4_port, Y => n68);
   U219 : INVX2 port map( A => bitCount_5_port, Y => n69);
   U220 : INVX2 port map( A => bitCount_6_port, Y => n70);
   U221 : INVX2 port map( A => n128, Y => DataReadyW);
   U222 : INVX2 port map( A => state2_1_port, Y => n72);
   U223 : INVX2 port map( A => n124, Y => DataReadyB);
   U224 : INVX2 port map( A => state2_0_port, Y => n74);

end SYN_A_InBlock;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity OUTPUT_BLOCK is

   port( CLK, RST, EN, SYNC, STB : in std_logic;  DATA : in std_logic_vector 
         (15 downto 0);  REQ, SDO : out std_logic);

end OUTPUT_BLOCK;

architecture SYN_sdo_arch of OUTPUT_BLOCK is

   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component HAX1
      port( A, B : in std_logic;  YC, YS : out std_logic);
   end component;
   
   component SET_N_SHIFT_16_0
      port( CLK, RST_N, SHIFT_ENABLE, SET_ENABLE : in std_logic;  DATA_IN : in 
            std_logic_vector (15 downto 0);  SHIFT_OUT : out std_logic);
   end component;
   
   component SET_N_SHIFT_16_1
      port( CLK, RST_N, SHIFT_ENABLE, SET_ENABLE : in std_logic;  DATA_IN : in 
            std_logic_vector (15 downto 0);  SHIFT_OUT : out std_logic);
   end component;
   
   component NOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND3X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI21X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component AOI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component AOI21X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component OR2X2
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component AND2X2
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component DFFSR
      port( D, CLK, R, S : in std_logic;  Q : out std_logic);
   end component;
   
   signal SDO_port, sns0_set, sns0_out, sns1_set, sns1_out, state_1_port, 
      state_0_port, bitcount_3_port, bitcount_2_port, bitcount_1_port, 
      bitcount_0_port, wordcount_5_port, wordcount_4_port, wordcount_3_port, 
      wordcount_2_port, wordcount_1_port, wordcount_0_port, N28, N62, N63, N64,
      N65, N66, indata_1_port, indata_0_port, prevstate_1_port, 
      prevstate_0_port, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, 
      n15, n16, n17, n18, n19, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57
      , n58, n59, n60, n61, n62_port, n63_port, n64_port, n65_port, n66_port, 
      n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81
      , n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, 
      n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108,
      n109, n110, n111, REQ_port, r76_carry_2_port, r76_carry_3_port, 
      r76_carry_4_port, r76_carry_5_port, n1, n2, n20, n21, n22, n23, n24, n25,
      n26, n27, n28_port, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39
      , n40, n41, n42, n43, n44, n45, n46, n47 : std_logic;

begin
   REQ <= REQ_port;
   SDO <= SDO_port;
   
   wordcount_reg_0_inst : DFFSR port map( D => n110, CLK => n1, R => RST, S => 
                           n19, Q => wordcount_0_port);
   state_reg_1_inst : DFFSR port map( D => n108, CLK => n1, R => RST, S => n18,
                           Q => state_1_port);
   state_reg_0_inst : DFFSR port map( D => n103, CLK => n1, R => RST, S => n17,
                           Q => state_0_port);
   bitcount_reg_0_inst : DFFSR port map( D => n107, CLK => n1, R => RST, S => 
                           n16, Q => bitcount_0_port);
   bitcount_reg_1_inst : DFFSR port map( D => n106, CLK => n1, R => RST, S => 
                           n15, Q => bitcount_1_port);
   bitcount_reg_2_inst : DFFSR port map( D => n105, CLK => n1, R => RST, S => 
                           n14, Q => bitcount_2_port);
   bitcount_reg_3_inst : DFFSR port map( D => n104, CLK => n1, R => RST, S => 
                           n13, Q => bitcount_3_port);
   wordcount_reg_1_inst : DFFSR port map( D => n99, CLK => n1, R => RST, S => 
                           n12, Q => wordcount_1_port);
   wordcount_reg_2_inst : DFFSR port map( D => n100, CLK => n1, R => RST, S => 
                           n11, Q => wordcount_2_port);
   wordcount_reg_3_inst : DFFSR port map( D => n101, CLK => n1, R => RST, S => 
                           n10, Q => wordcount_3_port);
   wordcount_reg_4_inst : DFFSR port map( D => n102, CLK => n1, R => RST, S => 
                           n9, Q => wordcount_4_port);
   wordcount_reg_5_inst : DFFSR port map( D => n109, CLK => n1, R => RST, S => 
                           n8, Q => wordcount_5_port);
   prevstate_reg_1_inst : DFFSR port map( D => state_1_port, CLK => n1, R => 
                           RST, S => n7, Q => prevstate_1_port);
   prevstate_reg_0_inst : DFFSR port map( D => state_0_port, CLK => n1, R => 
                           RST, S => n6, Q => prevstate_0_port);
   indata_reg_0_inst : DFFSR port map( D => n98, CLK => n1, R => n5, S => RST, 
                           Q => indata_0_port);
   indata_reg_1_inst : DFFSR port map( D => n97, CLK => n1, R => RST, S => n4, 
                           Q => indata_1_port);
   sdo_int_f_reg : DFFSR port map( D => n96, CLK => n1, R => RST, S => n3, Q =>
                           SDO_port);
   n3 <= '1';
   n4 <= '1';
   n5 <= '1';
   n6 <= '1';
   n7 <= '1';
   n8 <= '1';
   n9 <= '1';
   n10 <= '1';
   n11 <= '1';
   n12 <= '1';
   n13 <= '1';
   n14 <= '1';
   n15 <= '1';
   n16 <= '1';
   n17 <= '1';
   n18 <= '1';
   n19 <= '1';
   U20 : AND2X2 port map( A => n70, B => SYNC, Y => n80);
   U21 : AND2X2 port map( A => n63_port, B => n53, Y => n86);
   U22 : OR2X2 port map( A => n91, B => n92, Y => n68);
   U51 : NOR2X1 port map( A => n46, B => n48, Y => sns1_set);
   U52 : NAND2X1 port map( A => n111, B => n45, Y => n48);
   U53 : NOR2X1 port map( A => n46, B => n49, Y => sns0_set);
   U54 : NAND2X1 port map( A => n26, B => n45, Y => n49);
   U55 : NAND2X1 port map( A => n50, B => n51, Y => n96);
   U56 : OAI21X1 port map( A => n52, B => n53, C => SDO_port, Y => n51);
   U57 : AOI22X1 port map( A => sns0_out, B => n111, C => sns1_out, D => N28, Y
                           => n50);
   U58 : NOR2X1 port map( A => n54, B => n44, Y => n97);
   U59 : OAI21X1 port map( A => n55, B => n56, C => n43, Y => n98);
   U60 : NOR2X1 port map( A => STB, B => n44, Y => n54);
   U61 : NAND2X1 port map( A => n45, B => n46, Y => n56);
   U62 : AOI22X1 port map( A => prevstate_0_port, B => n57, C => 
                           prevstate_1_port, D => n58, Y => n55);
   U63 : OAI21X1 port map( A => prevstate_0_port, B => n31, C => state_1_port, 
                           Y => n58);
   U64 : OAI21X1 port map( A => prevstate_1_port, B => n27, C => state_0_port, 
                           Y => n57);
   U65 : OAI21X1 port map( A => n23, B => n38, C => n59, Y => n99);
   U66 : NAND2X1 port map( A => N62, B => n20, Y => n59);
   U67 : OAI21X1 port map( A => n23, B => n39, C => n60, Y => n100);
   U68 : NAND2X1 port map( A => N63, B => n20, Y => n60);
   U69 : OAI21X1 port map( A => n23, B => n40, C => n61, Y => n101);
   U70 : NAND2X1 port map( A => N64, B => n20, Y => n61);
   U71 : OAI21X1 port map( A => n23, B => n41, C => n62_port, Y => n102);
   U72 : NAND2X1 port map( A => N65, B => n20, Y => n62_port);
   U73 : OAI21X1 port map( A => n31, B => n63_port, C => n64_port, Y => n103);
   U74 : AOI22X1 port map( A => EN, B => n65_port, C => n52, D => n63_port, Y 
                           => n64_port);
   U75 : OAI21X1 port map( A => n32, B => n28_port, C => n66_port, Y => 
                           n65_port);
   U76 : NAND2X1 port map( A => n67, B => n63_port, Y => n66_port);
   U77 : OAI21X1 port map( A => n22, B => n68, C => n26, Y => n67);
   U78 : OAI21X1 port map( A => n69, B => n70, C => n71, Y => n104);
   U79 : OAI21X1 port map( A => n72, B => n30, C => bitcount_3_port, Y => n71);
   U80 : NOR2X1 port map( A => n73, B => n69, Y => n72);
   U81 : OAI21X1 port map( A => n74, B => n36, C => n75, Y => n105);
   U82 : NAND3X1 port map( A => n76, B => n36, C => n25, Y => n75);
   U83 : AOI21X1 port map( A => n25, B => n33, C => n30, Y => n74);
   U84 : OAI21X1 port map( A => n77, B => n35, C => n78, Y => n106);
   U85 : NAND3X1 port map( A => bitcount_0_port, B => n35, C => n25, Y => n78);
   U86 : AOI21X1 port map( A => n25, B => n34, C => n30, Y => n77);
   U87 : OAI22X1 port map( A => n79, B => n34, C => bitcount_0_port, D => n69, 
                           Y => n107);
   U88 : OAI21X1 port map( A => n80, B => n81, C => n79, Y => n69);
   U89 : NAND2X1 port map( A => n82, B => n83, Y => n81);
   U90 : NOR2X1 port map( A => n47, B => n52, Y => n79);
   U91 : OAI22X1 port map( A => n27, B => n63_port, C => n47, D => n84, Y => 
                           n108);
   U92 : AOI22X1 port map( A => n68, B => n85, C => n86, D => n32, Y => n84);
   U93 : NAND2X1 port map( A => n73, B => n37, Y => n70);
   U94 : OAI21X1 port map( A => EN, B => n52, C => n87, Y => n63_port);
   U95 : OAI21X1 port map( A => SYNC, B => n28_port, C => n24, Y => n87);
   U96 : OAI21X1 port map( A => n23, B => n42, C => n88, Y => n109);
   U97 : NAND2X1 port map( A => N66, B => n20, Y => n88);
   U98 : OAI21X1 port map( A => n23, B => n21, C => n89, Y => n110);
   U99 : NAND2X1 port map( A => n21, B => n20, Y => n89);
   U100 : NAND3X1 port map( A => n68, B => n85, C => n23, Y => n90);
   U101 : NAND2X1 port map( A => n22, B => n26, Y => n85);
   U102 : NAND3X1 port map( A => wordcount_3_port, B => wordcount_1_port, C => 
                           wordcount_5_port, Y => n92);
   U103 : NAND3X1 port map( A => n39, B => n41, C => n21, Y => n91);
   U104 : NAND3X1 port map( A => n29, B => n28_port, C => n24, Y => n93);
   U105 : NAND3X1 port map( A => n82, B => n83, C => EN, Y => n94);
   U106 : NAND2X1 port map( A => N28, B => n95, Y => n83);
   U107 : NAND2X1 port map( A => n111, B => n95, Y => n82);
   U108 : NAND2X1 port map( A => bitcount_3_port, B => n73, Y => n95);
   U109 : NOR2X1 port map( A => n36, B => n33, Y => n73);
   U110 : NOR2X1 port map( A => n35, B => n34, Y => n76);
   U111 : NOR2X1 port map( A => n31, B => state_1_port, Y => n53);
   U112 : NOR2X1 port map( A => state_1_port, B => state_0_port, Y => n52);
   U113 : NOR2X1 port map( A => n27, B => state_0_port, Y => n111);
   U114 : NOR2X1 port map( A => n45, B => indata_1_port, Y => REQ_port);
   U115 : NOR2X1 port map( A => n31, B => n27, Y => N28);
   SNS_0 : SET_N_SHIFT_16_1 port map( CLK => n1, RST_N => RST, SHIFT_ENABLE => 
                           n111, SET_ENABLE => sns0_set, DATA_IN(15) => 
                           DATA(15), DATA_IN(14) => DATA(14), DATA_IN(13) => 
                           DATA(13), DATA_IN(12) => DATA(12), DATA_IN(11) => 
                           DATA(11), DATA_IN(10) => DATA(10), DATA_IN(9) => 
                           DATA(9), DATA_IN(8) => DATA(8), DATA_IN(7) => 
                           DATA(7), DATA_IN(6) => DATA(6), DATA_IN(5) => 
                           DATA(5), DATA_IN(4) => DATA(4), DATA_IN(3) => 
                           DATA(3), DATA_IN(2) => DATA(2), DATA_IN(1) => 
                           DATA(1), DATA_IN(0) => DATA(0), SHIFT_OUT => 
                           sns0_out);
   SNS_1 : SET_N_SHIFT_16_0 port map( CLK => n1, RST_N => RST, SHIFT_ENABLE => 
                           N28, SET_ENABLE => sns1_set, DATA_IN(15) => DATA(15)
                           , DATA_IN(14) => DATA(14), DATA_IN(13) => DATA(13), 
                           DATA_IN(12) => DATA(12), DATA_IN(11) => DATA(11), 
                           DATA_IN(10) => DATA(10), DATA_IN(9) => DATA(9), 
                           DATA_IN(8) => DATA(8), DATA_IN(7) => DATA(7), 
                           DATA_IN(6) => DATA(6), DATA_IN(5) => DATA(5), 
                           DATA_IN(4) => DATA(4), DATA_IN(3) => DATA(3), 
                           DATA_IN(2) => DATA(2), DATA_IN(1) => DATA(1), 
                           DATA_IN(0) => DATA(0), SHIFT_OUT => sns1_out);
   r76_U1_1_1 : HAX1 port map( A => wordcount_1_port, B => wordcount_0_port, YC
                           => r76_carry_2_port, YS => N62);
   r76_U1_1_2 : HAX1 port map( A => wordcount_2_port, B => r76_carry_2_port, YC
                           => r76_carry_3_port, YS => N63);
   r76_U1_1_3 : HAX1 port map( A => wordcount_3_port, B => r76_carry_3_port, YC
                           => r76_carry_4_port, YS => N64);
   r76_U1_1_4 : HAX1 port map( A => wordcount_4_port, B => r76_carry_4_port, YC
                           => r76_carry_5_port, YS => N65);
   U23 : INVX2 port map( A => n2, Y => n1);
   U24 : INVX2 port map( A => CLK, Y => n2);
   U25 : XOR2X1 port map( A => r76_carry_5_port, B => wordcount_5_port, Y => 
                           N66);
   U26 : INVX2 port map( A => n90, Y => n20);
   U27 : INVX2 port map( A => wordcount_0_port, Y => n21);
   U28 : INVX2 port map( A => N28, Y => n22);
   U29 : INVX2 port map( A => n93, Y => n23);
   U30 : INVX2 port map( A => n94, Y => n24);
   U31 : INVX2 port map( A => n69, Y => n25);
   U32 : INVX2 port map( A => n111, Y => n26);
   U33 : INVX2 port map( A => state_1_port, Y => n27);
   U34 : INVX2 port map( A => n53, Y => n28_port);
   U35 : INVX2 port map( A => n52, Y => n29);
   U36 : INVX2 port map( A => n79, Y => n30);
   U37 : INVX2 port map( A => state_0_port, Y => n31);
   U38 : INVX2 port map( A => n70, Y => n32);
   U39 : INVX2 port map( A => n76, Y => n33);
   U40 : INVX2 port map( A => bitcount_0_port, Y => n34);
   U41 : INVX2 port map( A => bitcount_1_port, Y => n35);
   U42 : INVX2 port map( A => bitcount_2_port, Y => n36);
   U43 : INVX2 port map( A => bitcount_3_port, Y => n37);
   U44 : INVX2 port map( A => wordcount_1_port, Y => n38);
   U45 : INVX2 port map( A => wordcount_2_port, Y => n39);
   U46 : INVX2 port map( A => wordcount_3_port, Y => n40);
   U47 : INVX2 port map( A => wordcount_4_port, Y => n41);
   U48 : INVX2 port map( A => wordcount_5_port, Y => n42);
   U49 : INVX2 port map( A => n54, Y => n43);
   U50 : INVX2 port map( A => REQ_port, Y => n44);
   U116 : INVX2 port map( A => indata_0_port, Y => n45);
   U117 : INVX2 port map( A => indata_1_port, Y => n46);
   U118 : INVX2 port map( A => EN, Y => n47);

end SYN_sdo_arch;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity MEMORY_CONTROLLER is

   port( CLK, RST : in std_logic;  EN, ERR, CRIT, REQ_Tx_DATA : out std_logic; 
         Tx_DATA_STB : in std_logic;  NEW_Rx_DATA : out std_logic;  Rx_DATA_STB
         : in std_logic;  ADDR : out std_logic_vector (11 downto 0);  DATA_in :
         in std_logic_vector (7 downto 0);  DATA_out : out std_logic_vector (7 
         downto 0);  RW, RE, WE, BUSY, OWN_MEM : out std_logic;  OUTDATA : out 
         std_logic_vector (15 downto 0);  OUTSTRB : out std_logic;  OUTREQ : in
         std_logic;  I0DATA : in std_logic_vector (15 downto 0);  I0DRW, I0DRB 
         : in std_logic;  I0STRB : out std_logic;  I1DATA : in std_logic_vector
         (15 downto 0);  I1DRW, I1DRB : in std_logic;  I1STRB : out std_logic; 
         SYNC : in std_logic);

end MEMORY_CONTROLLER;

architecture SYN_mcu_arch of MEMORY_CONTROLLER is

   component INVX1
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component MUX2X1
      port( B, A, S : in std_logic;  Y : out std_logic);
   end component;
   
   component NOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component OR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND3X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI21X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component NOR3X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component AOI21X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component AOI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component AND2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component AND2X2
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component XNOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component OR2X2
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component BUFX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component INVX4
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component HAX1
      port( A, B : in std_logic;  YC, YS : out std_logic);
   end component;
   
   component MEMORY_CONTROLLER_DW01_inc_9
      port( A : in std_logic_vector (6 downto 0);  SUM : out std_logic_vector 
            (6 downto 0));
   end component;
   
   component MEMORY_CONTROLLER_DW01_inc_6
      port( A : in std_logic_vector (11 downto 0);  SUM : out std_logic_vector 
            (11 downto 0));
   end component;
   
   component MEMORY_CONTROLLER_DW01_inc_5
      port( A : in std_logic_vector (11 downto 0);  SUM : out std_logic_vector 
            (11 downto 0));
   end component;
   
   component MEMORY_CONTROLLER_DW01_inc_4
      port( A : in std_logic_vector (11 downto 0);  SUM : out std_logic_vector 
            (11 downto 0));
   end component;
   
   component MEMORY_CONTROLLER_DW01_inc_3
      port( A : in std_logic_vector (11 downto 0);  SUM : out std_logic_vector 
            (11 downto 0));
   end component;
   
   component MEMORY_CONTROLLER_DW01_inc_2
      port( A : in std_logic_vector (11 downto 0);  SUM : out std_logic_vector 
            (11 downto 0));
   end component;
   
   component MEMORY_CONTROLLER_DW01_inc_1
      port( A : in std_logic_vector (11 downto 0);  SUM : out std_logic_vector 
            (11 downto 0));
   end component;
   
   component MEMORY_CONTROLLER_DW01_inc_0
      port( A : in std_logic_vector (11 downto 0);  SUM : out std_logic_vector 
            (11 downto 0));
   end component;
   
   component DFFSR
      port( D, CLK, R, S : in std_logic;  Q : out std_logic);
   end component;
   
   signal EN_port, ADDR_11_port, ADDR_10_port, ADDR_9_port, ADDR_8_port, 
      ADDR_7_port, ADDR_6_port, ADDR_5_port, ADDR_4_port, ADDR_3_port, 
      ADDR_2_port, ADDR_1_port, ADDR_0_port, DATA_out_7_port, DATA_out_6_port, 
      DATA_out_5_port, DATA_out_4_port, DATA_out_3_port, DATA_out_2_port, 
      DATA_out_1_port, DATA_out_0_port, WE_port, OUTDATA_15_port, 
      OUTDATA_14_port, OUTDATA_13_port, OUTDATA_12_port, OUTDATA_11_port, 
      OUTDATA_10_port, OUTDATA_9_port, OUTDATA_8_port, OUTDATA_7_port, 
      OUTDATA_6_port, OUTDATA_5_port, OUTDATA_4_port, OUTDATA_3_port, 
      OUTDATA_2_port, OUTDATA_1_port, OUTDATA_0_port, mainState_4_port, 
      mainState_3_port, mainState_2_port, mainState_1_port, mainState_0_port, 
      outwait_2_port, outwait_1_port, outwait_0_port, I0wait_1_port, 
      I0wait_0_port, I1wait_1_port, I1wait_0_port, CORBaddr_11_port, 
      CORBaddr_10_port, CORBaddr_9_port, CORBaddr_8_port, CORBaddr_7_port, 
      CORBaddr_6_port, CORBaddr_5_port, CORBaddr_4_port, CORBaddr_3_port, 
      CORBaddr_2_port, CORBaddr_1_port, CORBaddr_0_port, RIRBaddr_11_port, 
      RIRBaddr_10_port, RIRBaddr_9_port, RIRBaddr_8_port, RIRBaddr_7_port, 
      RIRBaddr_6_port, RIRBaddr_5_port, RIRBaddr_4_port, RIRBaddr_3_port, 
      RIRBaddr_2_port, RIRBaddr_1_port, RIRBaddr_0_port, RIRB1addr_11_port, 
      RIRB1addr_10_port, RIRB1addr_9_port, RIRB1addr_8_port, RIRB1addr_7_port, 
      RIRB1addr_6_port, RIRB1addr_5_port, RIRB1addr_4_port, RIRB1addr_3_port, 
      RIRB1addr_2_port, RIRB1addr_1_port, RIRB1addr_0_port, OUTaddr_11_port, 
      OUTaddr_10_port, OUTaddr_9_port, OUTaddr_8_port, OUTaddr_7_port, 
      OUTaddr_6_port, OUTaddr_5_port, OUTaddr_4_port, OUTaddr_3_port, 
      OUTaddr_2_port, OUTaddr_1_port, OUTaddr_0_port, OUT2addr_11_port, 
      OUT2addr_10_port, OUT2addr_9_port, OUT2addr_8_port, OUT2addr_7_port, 
      OUT2addr_6_port, OUT2addr_5_port, OUT2addr_4_port, OUT2addr_3_port, 
      OUT2addr_2_port, OUT2addr_1_port, OUT2addr_0_port, IN0addr_11_port, 
      IN0addr_10_port, IN0addr_9_port, IN0addr_8_port, IN0addr_7_port, 
      IN0addr_6_port, IN0addr_5_port, IN0addr_4_port, IN0addr_3_port, 
      IN0addr_2_port, IN0addr_1_port, IN0addr_0_port, IN1addr_11_port, 
      IN1addr_10_port, IN1addr_9_port, IN1addr_8_port, IN1addr_7_port, 
      IN1addr_6_port, IN1addr_5_port, IN1addr_4_port, IN1addr_3_port, 
      IN1addr_2_port, IN1addr_1_port, IN1addr_0_port, outByteCount_6_port, 
      outByteCount_5_port, outByteCount_4_port, outByteCount_3_port, 
      outByteCount_2_port, outByteCount_1_port, outByteCount_0_port, 
      IN0ByteCount_5_port, IN0ByteCount_4_port, IN0ByteCount_3_port, 
      IN0ByteCount_2_port, IN0ByteCount_1_port, IN0ByteCount_0_port, 
      IN1ByteCount_5_port, IN1ByteCount_4_port, IN1ByteCount_3_port, 
      IN1ByteCount_2_port, IN1ByteCount_1_port, IN1ByteCount_0_port, 
      SYNCcount_3_port, SYNCcount_2_port, SYNCcount_1_port, miniOUTstate_1_port
      , miniOUTstate_0_port, miniINstate_1_port, miniINstate_0_port, OUThold, 
      nextMiniOUTstate_1_port, nextMiniOUTstate_0_port, nextMiniINstate_1_port,
      nextMiniINstate_0_port, nextRW_i, nextBUSY_i, nextRE_i, nextOUThold, N286
      , N287, N288, N289, N290, N291, N292, N306, N307, N308, N309, N310, N311,
      N312, N330, N331, N332, N333, N334, N335, N337, N400, N401, N402, N403, 
      N404, N405, N406, N407, N408, N409, N410, N411, N417, N418, N419, N420, 
      N421, N422, N423, N424, N425, N426, N427, N428, N432, N433, N434, N435, 
      N436, N437, N438, N439, N440, N441, N442, N443, N630, N660, N661, N662, 
      N663, N664, N672, N673, N674, N675, N676, N677, N684, N685, N686, N687, 
      N688, N689, N690, N691, N734, N735, N736, N737, N738, N739, N740, N741, 
      N742, N743, N744, N745, N751, N752, N753, N754, N755, N756, N757, N758, 
      N759, N760, N761, N762, N867, N897, N898, N899, N900, N901, N911, N915, 
      N921, N922, N923, N924, N925, N926, N929, N971, N972, N973, N974, N975, 
      N976, N977, N978, N979, N980, N981, N982, N988, N989, N990, N991, N992, 
      N993, N994, N995, N996, N997, N998, N999, N1113, N1124, N1495, N1497, 
      N1499, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, 
      n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, 
      n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, 
      n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, 
      n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, 
      n180, n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, 
      n192, n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, 
      n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, 
      n216, n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, 
      n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, 
      n240, n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, 
      n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, 
      n264, n265, n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, 
      n276, n277, n278, n279, n280, n281, n282, n283, n284, n285, n286_port, 
      n899_port, n900_port, n901_port, n902, n903, n904, n905, n906, n907, n908
      , n909, n910, n911_port, n912, n913, n914, n915_port, n916, n917, n918, 
      n919, n920, n921_port, n922_port, n923_port, n924_port, n925_port, 
      n926_port, n927, n928, n929_port, n930, n931, n932, n933, n934, n935, 
      n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946, n947, 
      n948, n949, n950, n951, n952, n953, n954, n955, n956, n957, n958, n959, 
      n960, n961, n962, n963, n964, n965, n966, n967, n968, n969, n970, 
      n971_port, n972_port, n973_port, n974_port, n975_port, n976_port, 
      n977_port, n978_port, n979_port, n980_port, n981_port, n982_port, n983, 
      n984, n985, n986, n987, n988_port, n989_port, n990_port, n991_port, 
      n992_port, n993_port, n994_port, n995_port, n996_port, n997_port, 
      n998_port, n999_port, n1000, n1001, n1002, n1003, n1004, n1005, n1006, 
      n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, 
      n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, 
      n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, 
      n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, 
      n1047, n1048, n1049, n1050, REQ_Tx_DATA_port, add_566_aco_carry_1_port, 
      add_566_aco_carry_2_port, add_566_aco_carry_3_port, 
      add_566_aco_carry_4_port, add_566_aco_carry_5_port, 
      add_566_aco_carry_6_port, add_566_aco_carry_7_port, 
      add_566_aco_carry_8_port, add_566_aco_carry_9_port, 
      add_566_aco_carry_10_port, add_563_aco_carry_1_port, 
      add_563_aco_carry_2_port, add_563_aco_carry_3_port, 
      add_563_aco_carry_4_port, add_563_aco_carry_5_port, 
      add_563_aco_carry_6_port, add_563_aco_carry_7_port, 
      add_563_aco_carry_8_port, add_563_aco_carry_9_port, 
      add_563_aco_carry_10_port, add_493_aco_carry_1_port, 
      add_493_aco_carry_2_port, add_493_aco_carry_3_port, 
      add_493_aco_carry_4_port, add_493_aco_carry_5_port, 
      add_493_aco_carry_6_port, add_493_aco_carry_7_port, 
      add_493_aco_carry_8_port, add_493_aco_carry_9_port, 
      add_493_aco_carry_10_port, add_490_aco_carry_1_port, 
      add_490_aco_carry_2_port, add_490_aco_carry_3_port, 
      add_490_aco_carry_4_port, add_490_aco_carry_5_port, 
      add_490_aco_carry_6_port, add_490_aco_carry_7_port, 
      add_490_aco_carry_8_port, add_490_aco_carry_9_port, 
      add_490_aco_carry_10_port, add_377_aco_carry_1_port, 
      add_377_aco_carry_2_port, add_377_aco_carry_3_port, 
      add_377_aco_carry_4_port, add_377_aco_carry_5_port, 
      add_377_aco_carry_6_port, add_377_aco_carry_7_port, 
      add_377_aco_carry_8_port, add_377_aco_carry_9_port, 
      add_377_aco_carry_10_port, add_377_aco_B_0_port, add_374_aco_carry_1_port
      , add_374_aco_carry_2_port, add_374_aco_carry_3_port, 
      add_374_aco_carry_4_port, add_374_aco_carry_5_port, 
      add_374_aco_carry_6_port, add_374_aco_carry_7_port, 
      add_374_aco_carry_8_port, add_374_aco_carry_9_port, 
      add_374_aco_carry_10_port, add_371_aco_carry_1_port, 
      add_371_aco_carry_2_port, add_371_aco_carry_3_port, 
      add_371_aco_carry_4_port, add_371_aco_carry_5_port, 
      add_371_aco_carry_6_port, add_371_aco_carry_7_port, 
      add_371_aco_carry_8_port, add_371_aco_carry_9_port, 
      add_371_aco_carry_10_port, add_371_aco_B_0_port, r317_carry_2_port, 
      r317_carry_3_port, r317_carry_4_port, r317_carry_5_port, 
      r308_carry_2_port, r308_carry_3_port, r308_carry_4_port, 
      r308_carry_5_port, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13
      , n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, 
      n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42
      , n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, 
      n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71
      , n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, 
      n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, 
      n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, 
      n112, n113, n114, n115, n116, n117, n118, n119, n120, n287_port, 
      n288_port, n289_port, n290_port, n291_port, n292_port, n293, n294, n295, 
      n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306_port, 
      n307_port, n308_port, n309_port, n310_port, n311_port, n312_port, n313, 
      n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, 
      n326, n327, n328, n329, n330_port, n331_port, n332_port, n333_port, 
      n334_port, n335_port, n336, n337_port, n338, n339, n340, n341, n342, n343
      , n344, n345, n346, n347, n348, n349, n350, n351, n352, n353, n354, n355,
      n356, n357, n358, n359, n360, n361, n362, n363, n364, n365, n366, n367, 
      n368, n369, n370, n371, n372, n373, n374, n375, n376, n377, n378, n379, 
      n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, n390, n391, 
      n392, n393, n394, n395, n396, n397, n398, n399, n400_port, n401_port, 
      n402_port, n403_port, n404_port, n405_port, n406_port, n407_port, 
      n408_port, n409_port, n410_port, n411_port, n412, n413, n414, n415, n416,
      n417_port, n418_port, n419_port, n420_port, n421_port, n422_port, 
      n423_port, n424_port, n425_port, n426_port, n427_port, n428_port, n429, 
      n430, n431, n432_port, n433_port, n434_port, n435_port, n436_port, 
      n437_port, n438_port, n439_port, n440_port, n441_port, n442_port, 
      n443_port, n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, 
      n454, n455, n456, n457, n458, n459, n460, n461, n462, n463, n464, n465, 
      n466, n467, n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, 
      n478, n479, n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, 
      n490, n491, n492, n493, n494, n495, n496, n497, n498, n499, n500, n501, 
      n502, n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, 
      n514, n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525, 
      n526, n527, n528, n529, n530, n531, n532, n533, n534, n535, n536, n537, 
      n538, n539, n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, 
      n550, n551, n552, n553, n554, n555, n556, n557, n558, n559, n560, n561, 
      n562, n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, n573, 
      n574, n575, n576, n577, n578, n579, n580, n581, n582, n583, n584, n585, 
      n586, n587, n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, 
      n598, n599, n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, 
      n610, n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621, 
      n622, n623, n624, n625, n626, n627, n628, n629, n630_port, n631, n632, 
      n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, 
      n645, n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, 
      n657, n658, n659, n660_port, n661_port, n662_port, n663_port, n664_port, 
      n665, n666, n667, n668, n669, n670, n671, n672_port, n673_port, n674_port
      , n675_port, n676_port, n677_port, n678, n679, n680, n681, n682, n683, 
      n684_port, n685_port, n686_port, n687_port, n688_port, n689_port, 
      n690_port, n691_port, n692, n693, n694, n695, n696, n697, n698, n699, 
      n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, 
      n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, 
      n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734_port, 
      n735_port, n736_port, n737_port, n738_port, n739_port, n740_port, 
      n741_port, n742_port, n743_port, n744_port, n745_port, n746, n747, n748, 
      n749, n750, n751_port, n752_port, n753_port, n754_port, n755_port, 
      n756_port, n757_port, n758_port, n759_port, n760_port, n761_port, 
      n762_port, n763, n764, n765, n766, n767, n768, n769, n770, n771, n772, 
      n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, 
      n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, 
      n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, 
      n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, 
      n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, 
      n833, NEW_Rx_DATA_port : std_logic;

begin
   EN <= EN_port;
   REQ_Tx_DATA <= REQ_Tx_DATA_port;
   NEW_Rx_DATA <= NEW_Rx_DATA_port;
   ADDR <= ( ADDR_11_port, ADDR_10_port, ADDR_9_port, ADDR_8_port, ADDR_7_port,
      ADDR_6_port, ADDR_5_port, ADDR_4_port, ADDR_3_port, ADDR_2_port, 
      ADDR_1_port, ADDR_0_port );
   DATA_out <= ( DATA_out_7_port, DATA_out_6_port, DATA_out_5_port, 
      DATA_out_4_port, DATA_out_3_port, DATA_out_2_port, DATA_out_1_port, 
      DATA_out_0_port );
   WE <= WE_port;
   OUTDATA <= ( OUTDATA_15_port, OUTDATA_14_port, OUTDATA_13_port, 
      OUTDATA_12_port, OUTDATA_11_port, OUTDATA_10_port, OUTDATA_9_port, 
      OUTDATA_8_port, OUTDATA_7_port, OUTDATA_6_port, OUTDATA_5_port, 
      OUTDATA_4_port, OUTDATA_3_port, OUTDATA_2_port, OUTDATA_1_port, 
      OUTDATA_0_port );
   
   SYNCcount_reg_3_inst : DFFSR port map( D => SYNC, CLK => CLK, R => n106, S 
                           => n286_port, Q => SYNCcount_3_port);
   SYNCcount_reg_2_inst : DFFSR port map( D => SYNC, CLK => CLK, R => n105, S 
                           => n285, Q => SYNCcount_2_port);
   SYNCcount_reg_1_inst : DFFSR port map( D => SYNC, CLK => CLK, R => n105, S 
                           => n284, Q => SYNCcount_1_port);
   OUThold_reg : DFFSR port map( D => nextOUThold, CLK => CLK, R => n105, S => 
                           n283, Q => OUThold);
   mainState_reg_0_inst : DFFSR port map( D => n1047, CLK => CLK, R => n282, S 
                           => n118, Q => mainState_0_port);
   mainState_reg_4_inst : DFFSR port map( D => n1050, CLK => CLK, R => n281, S 
                           => n118, Q => mainState_4_port);
   I1wait_reg_0_inst : DFFSR port map( D => n997_port, CLK => CLK, R => n105, S
                           => n280, Q => I1wait_0_port);
   I1wait_reg_1_inst : DFFSR port map( D => n996_port, CLK => CLK, R => n105, S
                           => n279, Q => I1wait_1_port);
   I1wait_reg_2_inst : DFFSR port map( D => n995_port, CLK => CLK, R => n105, S
                           => n278, Q => N1124);
   mainState_reg_2_inst : DFFSR port map( D => n1046, CLK => CLK, R => n105, S 
                           => n277, Q => mainState_2_port);
   mainState_reg_3_inst : DFFSR port map( D => n1048, CLK => CLK, R => n105, S 
                           => n276, Q => mainState_3_port);
   mainState_reg_1_inst : DFFSR port map( D => n1049, CLK => CLK, R => n105, S 
                           => n275, Q => mainState_1_port);
   I0wait_reg_0_inst : DFFSR port map( D => n1000, CLK => CLK, R => n105, S => 
                           n274, Q => I0wait_0_port);
   I0wait_reg_1_inst : DFFSR port map( D => n999_port, CLK => CLK, R => n105, S
                           => n273, Q => I0wait_1_port);
   I0wait_reg_2_inst : DFFSR port map( D => n998_port, CLK => CLK, R => n106, S
                           => n272, Q => N1113);
   IN0ByteCount_reg_5_inst : DFFSR port map( D => n989_port, CLK => CLK, R => 
                           n106, S => n271, Q => IN0ByteCount_5_port);
   IN0ByteCount_reg_0_inst : DFFSR port map( D => n994_port, CLK => CLK, R => 
                           n106, S => n270, Q => IN0ByteCount_0_port);
   IN0ByteCount_reg_1_inst : DFFSR port map( D => n993_port, CLK => CLK, R => 
                           n106, S => n269, Q => IN0ByteCount_1_port);
   IN0ByteCount_reg_2_inst : DFFSR port map( D => n992_port, CLK => CLK, R => 
                           n106, S => n268, Q => IN0ByteCount_2_port);
   IN0ByteCount_reg_3_inst : DFFSR port map( D => n991_port, CLK => CLK, R => 
                           n106, S => n267, Q => IN0ByteCount_3_port);
   IN0ByteCount_reg_4_inst : DFFSR port map( D => n990_port, CLK => CLK, R => 
                           n110, S => n266, Q => IN0ByteCount_4_port);
   RIRBaddr_reg_11_inst : DFFSR port map( D => n977_port, CLK => CLK, R => n106
                           , S => n265, Q => RIRBaddr_11_port);
   RIRBaddr_reg_10_inst : DFFSR port map( D => n978_port, CLK => CLK, R => n106
                           , S => n264, Q => RIRBaddr_10_port);
   RIRBaddr_reg_0_inst : DFFSR port map( D => n988_port, CLK => CLK, R => n263,
                           S => n117, Q => RIRBaddr_0_port);
   RIRBaddr_reg_1_inst : DFFSR port map( D => n987, CLK => CLK, R => n262, S =>
                           n117, Q => RIRBaddr_1_port);
   RIRBaddr_reg_2_inst : DFFSR port map( D => n986, CLK => CLK, R => n261, S =>
                           n117, Q => RIRBaddr_2_port);
   RIRBaddr_reg_3_inst : DFFSR port map( D => n985, CLK => CLK, R => n260, S =>
                           n117, Q => RIRBaddr_3_port);
   RIRBaddr_reg_4_inst : DFFSR port map( D => n984, CLK => CLK, R => n259, S =>
                           n118, Q => RIRBaddr_4_port);
   RIRBaddr_reg_5_inst : DFFSR port map( D => n983, CLK => CLK, R => n258, S =>
                           n117, Q => RIRBaddr_5_port);
   RIRBaddr_reg_6_inst : DFFSR port map( D => n982_port, CLK => CLK, R => n106,
                           S => n257, Q => RIRBaddr_6_port);
   RIRBaddr_reg_7_inst : DFFSR port map( D => n981_port, CLK => CLK, R => n106,
                           S => n256, Q => RIRBaddr_7_port);
   RIRBaddr_reg_8_inst : DFFSR port map( D => n980_port, CLK => CLK, R => n106,
                           S => n255, Q => RIRBaddr_8_port);
   RIRBaddr_reg_9_inst : DFFSR port map( D => n979_port, CLK => CLK, R => n107,
                           S => n254, Q => RIRBaddr_9_port);
   IN0addr_reg_0_inst : DFFSR port map( D => n976_port, CLK => CLK, R => n253, 
                           S => n117, Q => IN0addr_0_port);
   IN0addr_reg_11_inst : DFFSR port map( D => n965, CLK => CLK, R => n107, S =>
                           n252, Q => IN0addr_11_port);
   IN0addr_reg_1_inst : DFFSR port map( D => n975_port, CLK => CLK, R => n251, 
                           S => n117, Q => IN0addr_1_port);
   IN0addr_reg_2_inst : DFFSR port map( D => n974_port, CLK => CLK, R => n250, 
                           S => n117, Q => IN0addr_2_port);
   IN0addr_reg_3_inst : DFFSR port map( D => n973_port, CLK => CLK, R => n249, 
                           S => n116, Q => IN0addr_3_port);
   IN0addr_reg_4_inst : DFFSR port map( D => n972_port, CLK => CLK, R => n248, 
                           S => n116, Q => IN0addr_4_port);
   IN0addr_reg_5_inst : DFFSR port map( D => n971_port, CLK => CLK, R => n247, 
                           S => n116, Q => IN0addr_5_port);
   IN0addr_reg_6_inst : DFFSR port map( D => n970, CLK => CLK, R => n246, S => 
                           n118, Q => IN0addr_6_port);
   IN0addr_reg_7_inst : DFFSR port map( D => n969, CLK => CLK, R => n245, S => 
                           n116, Q => IN0addr_7_port);
   IN0addr_reg_8_inst : DFFSR port map( D => n968, CLK => CLK, R => n107, S => 
                           n244, Q => IN0addr_8_port);
   IN0addr_reg_9_inst : DFFSR port map( D => n967, CLK => CLK, R => n107, S => 
                           n243, Q => IN0addr_9_port);
   IN0addr_reg_10_inst : DFFSR port map( D => n966, CLK => CLK, R => n107, S =>
                           n242, Q => IN0addr_10_port);
   outwait_reg_1_inst : DFFSR port map( D => n1002, CLK => CLK, R => n107, S =>
                           n241, Q => outwait_1_port);
   outwait_reg_0_inst : DFFSR port map( D => n833, CLK => CLK, R => n107, S => 
                           n240, Q => outwait_0_port);
   outwait_reg_2_inst : DFFSR port map( D => n1001, CLK => CLK, R => n107, S =>
                           n239, Q => outwait_2_port);
   EN_i_reg : DFFSR port map( D => n832, CLK => CLK, R => n107, S => n238, Q =>
                           EN_port);
   outByteCount_reg_6_inst : DFFSR port map( D => n1039, CLK => CLK, R => n107,
                           S => n237, Q => outByteCount_6_port);
   outByteCount_reg_5_inst : DFFSR port map( D => n1040, CLK => CLK, R => n107,
                           S => n236, Q => outByteCount_5_port);
   outByteCount_reg_0_inst : DFFSR port map( D => n1045, CLK => CLK, R => n107,
                           S => n235, Q => outByteCount_0_port);
   outByteCount_reg_1_inst : DFFSR port map( D => n1044, CLK => CLK, R => n108,
                           S => n234, Q => outByteCount_1_port);
   outByteCount_reg_2_inst : DFFSR port map( D => n1043, CLK => CLK, R => n108,
                           S => n233, Q => outByteCount_2_port);
   outByteCount_reg_3_inst : DFFSR port map( D => n1042, CLK => CLK, R => n108,
                           S => n232, Q => outByteCount_3_port);
   outByteCount_reg_4_inst : DFFSR port map( D => n1041, CLK => CLK, R => n108,
                           S => n231, Q => outByteCount_4_port);
   CORBaddr_reg_0_inst : DFFSR port map( D => n1038, CLK => CLK, R => n108, S 
                           => n230, Q => CORBaddr_0_port);
   CORBaddr_reg_11_inst : DFFSR port map( D => n1027, CLK => CLK, R => n108, S 
                           => n229, Q => CORBaddr_11_port);
   CORBaddr_reg_1_inst : DFFSR port map( D => n1037, CLK => CLK, R => n108, S 
                           => n228, Q => CORBaddr_1_port);
   CORBaddr_reg_2_inst : DFFSR port map( D => n1036, CLK => CLK, R => n108, S 
                           => n227, Q => CORBaddr_2_port);
   CORBaddr_reg_3_inst : DFFSR port map( D => n1035, CLK => CLK, R => n108, S 
                           => n226, Q => CORBaddr_3_port);
   CORBaddr_reg_4_inst : DFFSR port map( D => n1034, CLK => CLK, R => n108, S 
                           => n225, Q => CORBaddr_4_port);
   CORBaddr_reg_5_inst : DFFSR port map( D => n1033, CLK => CLK, R => n108, S 
                           => n224, Q => CORBaddr_5_port);
   CORBaddr_reg_6_inst : DFFSR port map( D => n1032, CLK => CLK, R => n108, S 
                           => n223, Q => CORBaddr_6_port);
   CORBaddr_reg_7_inst : DFFSR port map( D => n1031, CLK => CLK, R => n109, S 
                           => n222, Q => CORBaddr_7_port);
   CORBaddr_reg_8_inst : DFFSR port map( D => n1030, CLK => CLK, R => n109, S 
                           => n221, Q => CORBaddr_8_port);
   CORBaddr_reg_9_inst : DFFSR port map( D => n1029, CLK => CLK, R => n109, S 
                           => n220, Q => CORBaddr_9_port);
   CORBaddr_reg_10_inst : DFFSR port map( D => n1028, CLK => CLK, R => n109, S 
                           => n219, Q => CORBaddr_10_port);
   OUT2addr_reg_11_inst : DFFSR port map( D => n1003, CLK => CLK, R => n109, S 
                           => n218, Q => OUT2addr_11_port);
   OUT2addr_reg_10_inst : DFFSR port map( D => n1004, CLK => CLK, R => n109, S 
                           => n217, Q => OUT2addr_10_port);
   OUT2addr_reg_0_inst : DFFSR port map( D => n1014, CLK => CLK, R => n216, S 
                           => n116, Q => OUT2addr_0_port);
   OUT2addr_reg_1_inst : DFFSR port map( D => n1013, CLK => CLK, R => n215, S 
                           => n116, Q => OUT2addr_1_port);
   OUT2addr_reg_2_inst : DFFSR port map( D => n1012, CLK => CLK, R => n214, S 
                           => n117, Q => OUT2addr_2_port);
   OUT2addr_reg_3_inst : DFFSR port map( D => n1011, CLK => CLK, R => n213, S 
                           => n116, Q => OUT2addr_3_port);
   OUT2addr_reg_4_inst : DFFSR port map( D => n1010, CLK => CLK, R => n212, S 
                           => n116, Q => OUT2addr_4_port);
   OUT2addr_reg_5_inst : DFFSR port map( D => n1009, CLK => CLK, R => n211, S 
                           => n116, Q => OUT2addr_5_port);
   OUT2addr_reg_6_inst : DFFSR port map( D => n1008, CLK => CLK, R => n109, S 
                           => n210, Q => OUT2addr_6_port);
   OUT2addr_reg_7_inst : DFFSR port map( D => n1007, CLK => CLK, R => n209, S 
                           => n116, Q => OUT2addr_7_port);
   OUT2addr_reg_8_inst : DFFSR port map( D => n1006, CLK => CLK, R => n109, S 
                           => n208, Q => OUT2addr_8_port);
   OUT2addr_reg_9_inst : DFFSR port map( D => n1005, CLK => CLK, R => n109, S 
                           => n207, Q => OUT2addr_9_port);
   OUTaddr_reg_0_inst : DFFSR port map( D => n1026, CLK => CLK, R => n206, S =>
                           n118, Q => OUTaddr_0_port);
   OUTaddr_reg_11_inst : DFFSR port map( D => n1015, CLK => CLK, R => n109, S 
                           => n205, Q => OUTaddr_11_port);
   OUTaddr_reg_1_inst : DFFSR port map( D => n1025, CLK => CLK, R => n204, S =>
                           n115, Q => OUTaddr_1_port);
   OUTaddr_reg_2_inst : DFFSR port map( D => n1024, CLK => CLK, R => n203, S =>
                           n115, Q => OUTaddr_2_port);
   OUTaddr_reg_3_inst : DFFSR port map( D => n1023, CLK => CLK, R => n202, S =>
                           n117, Q => OUTaddr_3_port);
   OUTaddr_reg_4_inst : DFFSR port map( D => n1022, CLK => CLK, R => n201, S =>
                           n115, Q => OUTaddr_4_port);
   OUTaddr_reg_5_inst : DFFSR port map( D => n1021, CLK => CLK, R => n200, S =>
                           n115, Q => OUTaddr_5_port);
   OUTaddr_reg_6_inst : DFFSR port map( D => n1020, CLK => CLK, R => n199, S =>
                           n115, Q => OUTaddr_6_port);
   OUTaddr_reg_7_inst : DFFSR port map( D => n1019, CLK => CLK, R => n109, S =>
                           n198, Q => OUTaddr_7_port);
   OUTaddr_reg_8_inst : DFFSR port map( D => n1018, CLK => CLK, R => n109, S =>
                           n197, Q => OUTaddr_8_port);
   OUTaddr_reg_9_inst : DFFSR port map( D => n1017, CLK => CLK, R => n110, S =>
                           n196, Q => OUTaddr_9_port);
   OUTaddr_reg_10_inst : DFFSR port map( D => n1016, CLK => CLK, R => n110, S 
                           => n195, Q => OUTaddr_10_port);
   IN1ByteCount_reg_5_inst : DFFSR port map( D => n959, CLK => CLK, R => n110, 
                           S => n194, Q => IN1ByteCount_5_port);
   IN1ByteCount_reg_0_inst : DFFSR port map( D => n964, CLK => CLK, R => n110, 
                           S => n193, Q => IN1ByteCount_0_port);
   IN1ByteCount_reg_1_inst : DFFSR port map( D => n963, CLK => CLK, R => n110, 
                           S => n192, Q => IN1ByteCount_1_port);
   IN1ByteCount_reg_2_inst : DFFSR port map( D => n962, CLK => CLK, R => n110, 
                           S => n191, Q => IN1ByteCount_2_port);
   IN1ByteCount_reg_3_inst : DFFSR port map( D => n961, CLK => CLK, R => n110, 
                           S => n190, Q => IN1ByteCount_3_port);
   IN1ByteCount_reg_4_inst : DFFSR port map( D => n960, CLK => CLK, R => n110, 
                           S => n189, Q => IN1ByteCount_4_port);
   RIRB1addr_reg_2_inst : DFFSR port map( D => n956, CLK => CLK, R => n188, S 
                           => n117, Q => RIRB1addr_2_port);
   RIRB1addr_reg_11_inst : DFFSR port map( D => n947, CLK => CLK, R => n110, S 
                           => n187, Q => RIRB1addr_11_port);
   RIRB1addr_reg_0_inst : DFFSR port map( D => n958, CLK => CLK, R => n110, S 
                           => n186, Q => RIRB1addr_0_port);
   RIRB1addr_reg_1_inst : DFFSR port map( D => n957, CLK => CLK, R => n111, S 
                           => n185, Q => RIRB1addr_1_port);
   RIRB1addr_reg_3_inst : DFFSR port map( D => n955, CLK => CLK, R => n110, S 
                           => n184, Q => RIRB1addr_3_port);
   RIRB1addr_reg_4_inst : DFFSR port map( D => n954, CLK => CLK, R => n111, S 
                           => n183, Q => RIRB1addr_4_port);
   RIRB1addr_reg_5_inst : DFFSR port map( D => n953, CLK => CLK, R => n111, S 
                           => n182, Q => RIRB1addr_5_port);
   RIRB1addr_reg_6_inst : DFFSR port map( D => n952, CLK => CLK, R => n181, S 
                           => n115, Q => RIRB1addr_6_port);
   RIRB1addr_reg_7_inst : DFFSR port map( D => n951, CLK => CLK, R => n111, S 
                           => n180, Q => RIRB1addr_7_port);
   RIRB1addr_reg_8_inst : DFFSR port map( D => n950, CLK => CLK, R => n111, S 
                           => n179, Q => RIRB1addr_8_port);
   RIRB1addr_reg_9_inst : DFFSR port map( D => n949, CLK => CLK, R => n111, S 
                           => n178, Q => RIRB1addr_9_port);
   RIRB1addr_reg_10_inst : DFFSR port map( D => n948, CLK => CLK, R => n111, S 
                           => n177, Q => RIRB1addr_10_port);
   IN1addr_reg_0_inst : DFFSR port map( D => n946, CLK => CLK, R => n176, S => 
                           n117, Q => IN1addr_0_port);
   IN1addr_reg_11_inst : DFFSR port map( D => n935, CLK => CLK, R => n112, S =>
                           n175, Q => IN1addr_11_port);
   IN1addr_reg_1_inst : DFFSR port map( D => n945, CLK => CLK, R => n174, S => 
                           n117, Q => IN1addr_1_port);
   IN1addr_reg_2_inst : DFFSR port map( D => n944, CLK => CLK, R => n173, S => 
                           n116, Q => IN1addr_2_port);
   IN1addr_reg_3_inst : DFFSR port map( D => n943, CLK => CLK, R => n172, S => 
                           n116, Q => IN1addr_3_port);
   IN1addr_reg_4_inst : DFFSR port map( D => n942, CLK => CLK, R => n171, S => 
                           n116, Q => IN1addr_4_port);
   IN1addr_reg_5_inst : DFFSR port map( D => n941, CLK => CLK, R => n170, S => 
                           n117, Q => IN1addr_5_port);
   IN1addr_reg_6_inst : DFFSR port map( D => n940, CLK => CLK, R => n111, S => 
                           n169, Q => IN1addr_6_port);
   IN1addr_reg_7_inst : DFFSR port map( D => n939, CLK => CLK, R => n112, S => 
                           n168, Q => IN1addr_7_port);
   IN1addr_reg_8_inst : DFFSR port map( D => n938, CLK => CLK, R => n167, S => 
                           n116, Q => IN1addr_8_port);
   IN1addr_reg_9_inst : DFFSR port map( D => n937, CLK => CLK, R => n111, S => 
                           n166, Q => IN1addr_9_port);
   IN1addr_reg_10_inst : DFFSR port map( D => n936, CLK => CLK, R => n112, S =>
                           n165, Q => IN1addr_10_port);
   outbuf_reg_15_inst : DFFSR port map( D => n934, CLK => CLK, R => n112, S => 
                           n164, Q => OUTDATA_15_port);
   outbuf_reg_14_inst : DFFSR port map( D => n933, CLK => CLK, R => n112, S => 
                           n163, Q => OUTDATA_14_port);
   outbuf_reg_13_inst : DFFSR port map( D => n932, CLK => CLK, R => n111, S => 
                           n162, Q => OUTDATA_13_port);
   outbuf_reg_12_inst : DFFSR port map( D => n931, CLK => CLK, R => n112, S => 
                           n161, Q => OUTDATA_12_port);
   outbuf_reg_11_inst : DFFSR port map( D => n930, CLK => CLK, R => n112, S => 
                           n160, Q => OUTDATA_11_port);
   outbuf_reg_10_inst : DFFSR port map( D => n929_port, CLK => CLK, R => n113, 
                           S => n159, Q => OUTDATA_10_port);
   outbuf_reg_9_inst : DFFSR port map( D => n928, CLK => CLK, R => n111, S => 
                           n158, Q => OUTDATA_9_port);
   outbuf_reg_8_inst : DFFSR port map( D => n927, CLK => CLK, R => n113, S => 
                           n157, Q => OUTDATA_8_port);
   outbuf_reg_7_inst : DFFSR port map( D => n926_port, CLK => CLK, R => n113, S
                           => n156, Q => OUTDATA_7_port);
   outbuf_reg_6_inst : DFFSR port map( D => n925_port, CLK => CLK, R => n113, S
                           => n155, Q => OUTDATA_6_port);
   outbuf_reg_5_inst : DFFSR port map( D => n924_port, CLK => CLK, R => n112, S
                           => n154, Q => OUTDATA_5_port);
   outbuf_reg_4_inst : DFFSR port map( D => n923_port, CLK => CLK, R => n113, S
                           => n153, Q => OUTDATA_4_port);
   outbuf_reg_3_inst : DFFSR port map( D => n922_port, CLK => CLK, R => n113, S
                           => n152, Q => OUTDATA_3_port);
   outbuf_reg_2_inst : DFFSR port map( D => n921_port, CLK => CLK, R => n112, S
                           => n151, Q => OUTDATA_2_port);
   outbuf_reg_1_inst : DFFSR port map( D => n920, CLK => CLK, R => n112, S => 
                           n150, Q => OUTDATA_1_port);
   outbuf_reg_0_inst : DFFSR port map( D => n919, CLK => CLK, R => n113, S => 
                           n149, Q => OUTDATA_0_port);
   data_out_i_reg_7_inst : DFFSR port map( D => n918, CLK => CLK, R => n113, S 
                           => n148, Q => DATA_out_7_port);
   data_out_i_reg_6_inst : DFFSR port map( D => n917, CLK => CLK, R => n114, S 
                           => n147, Q => DATA_out_6_port);
   data_out_i_reg_5_inst : DFFSR port map( D => n916, CLK => CLK, R => n113, S 
                           => n146, Q => DATA_out_5_port);
   data_out_i_reg_4_inst : DFFSR port map( D => n915_port, CLK => CLK, R => 
                           n114, S => n145, Q => DATA_out_4_port);
   data_out_i_reg_3_inst : DFFSR port map( D => n914, CLK => CLK, R => n114, S 
                           => n144, Q => DATA_out_3_port);
   data_out_i_reg_2_inst : DFFSR port map( D => n913, CLK => CLK, R => n114, S 
                           => n143, Q => DATA_out_2_port);
   data_out_i_reg_1_inst : DFFSR port map( D => n912, CLK => CLK, R => n114, S 
                           => n142, Q => DATA_out_1_port);
   data_out_i_reg_0_inst : DFFSR port map( D => n911_port, CLK => CLK, R => 
                           n114, S => n141, Q => DATA_out_0_port);
   address_i_reg_11_inst : DFFSR port map( D => n899_port, CLK => CLK, R => 
                           n111, S => n140, Q => ADDR_11_port);
   address_i_reg_10_inst : DFFSR port map( D => n900_port, CLK => CLK, R => 
                           n114, S => n139, Q => ADDR_10_port);
   address_i_reg_9_inst : DFFSR port map( D => n901_port, CLK => CLK, R => n113
                           , S => n138, Q => ADDR_9_port);
   address_i_reg_8_inst : DFFSR port map( D => n902, CLK => CLK, R => n114, S 
                           => n137, Q => ADDR_8_port);
   address_i_reg_7_inst : DFFSR port map( D => n903, CLK => CLK, R => n113, S 
                           => n136, Q => ADDR_7_port);
   address_i_reg_6_inst : DFFSR port map( D => n904, CLK => CLK, R => n114, S 
                           => n135, Q => ADDR_6_port);
   address_i_reg_5_inst : DFFSR port map( D => n905, CLK => CLK, R => n114, S 
                           => n134, Q => ADDR_5_port);
   address_i_reg_4_inst : DFFSR port map( D => n906, CLK => CLK, R => n114, S 
                           => n133, Q => ADDR_4_port);
   address_i_reg_3_inst : DFFSR port map( D => n907, CLK => CLK, R => n113, S 
                           => n132, Q => ADDR_3_port);
   address_i_reg_2_inst : DFFSR port map( D => n908, CLK => CLK, R => n115, S 
                           => n131, Q => ADDR_2_port);
   address_i_reg_1_inst : DFFSR port map( D => n909, CLK => CLK, R => n115, S 
                           => n130, Q => ADDR_1_port);
   address_i_reg_0_inst : DFFSR port map( D => n910, CLK => CLK, R => n112, S 
                           => n129, Q => ADDR_0_port);
   miniOUTstate_reg_0_inst : DFFSR port map( D => nextMiniOUTstate_0_port, CLK 
                           => CLK, R => n114, S => n128, Q => 
                           miniOUTstate_0_port);
   miniOUTstate_reg_1_inst : DFFSR port map( D => nextMiniOUTstate_1_port, CLK 
                           => CLK, R => n115, S => n127, Q => 
                           miniOUTstate_1_port);
   miniINstate_reg_0_inst : DFFSR port map( D => nextMiniINstate_0_port, CLK =>
                           CLK, R => n115, S => n126, Q => miniINstate_0_port);
   miniINstate_reg_1_inst : DFFSR port map( D => nextMiniINstate_1_port, CLK =>
                           CLK, R => n115, S => n125, Q => miniINstate_1_port);
   RW_i_reg : DFFSR port map( D => nextRW_i, CLK => CLK, R => n115, S => n124, 
                           Q => RW);
   BUSY_i_reg : DFFSR port map( D => nextBUSY_i, CLK => CLK, R => n115, S => 
                           n123, Q => BUSY);
   OWNMEM_i_reg : DFFSR port map( D => n831, CLK => CLK, R => n112, S => n122, 
                           Q => OWN_MEM);
   RE_i_reg : DFFSR port map( D => nextRE_i, CLK => CLK, R => n105, S => n121, 
                           Q => RE);
   n121 <= '1';
   n122 <= '1';
   n123 <= '1';
   n124 <= '1';
   n125 <= '1';
   n126 <= '1';
   n127 <= '1';
   n128 <= '1';
   n129 <= '1';
   n130 <= '1';
   n131 <= '1';
   n132 <= '1';
   n133 <= '1';
   n134 <= '1';
   n135 <= '1';
   n136 <= '1';
   n137 <= '1';
   n138 <= '1';
   n139 <= '1';
   n140 <= '1';
   n141 <= '1';
   n142 <= '1';
   n143 <= '1';
   n144 <= '1';
   n145 <= '1';
   n146 <= '1';
   n147 <= '1';
   n148 <= '1';
   n149 <= '1';
   n150 <= '1';
   n151 <= '1';
   n152 <= '1';
   n153 <= '1';
   n154 <= '1';
   n155 <= '1';
   n156 <= '1';
   n157 <= '1';
   n158 <= '1';
   n159 <= '1';
   n160 <= '1';
   n161 <= '1';
   n162 <= '1';
   n163 <= '1';
   n164 <= '1';
   n165 <= '1';
   n166 <= '1';
   n167 <= '1';
   n168 <= '1';
   n169 <= '1';
   n170 <= '1';
   n171 <= '1';
   n172 <= '1';
   n173 <= '1';
   n174 <= '1';
   n175 <= '1';
   n176 <= '1';
   n177 <= '1';
   n178 <= '1';
   n179 <= '1';
   n180 <= '1';
   n181 <= '1';
   n182 <= '1';
   n183 <= '1';
   n184 <= '1';
   n185 <= '1';
   n186 <= '1';
   n187 <= '1';
   n188 <= '1';
   n189 <= '1';
   n190 <= '1';
   n191 <= '1';
   n192 <= '1';
   n193 <= '1';
   n194 <= '1';
   n195 <= '1';
   n196 <= '1';
   n197 <= '1';
   n198 <= '1';
   n199 <= '1';
   n200 <= '1';
   n201 <= '1';
   n202 <= '1';
   n203 <= '1';
   n204 <= '1';
   n205 <= '1';
   n206 <= '1';
   n207 <= '1';
   n208 <= '1';
   n209 <= '1';
   n210 <= '1';
   n211 <= '1';
   n212 <= '1';
   n213 <= '1';
   n214 <= '1';
   n215 <= '1';
   n216 <= '1';
   n217 <= '1';
   n218 <= '1';
   n219 <= '1';
   n220 <= '1';
   n221 <= '1';
   n222 <= '1';
   n223 <= '1';
   n224 <= '1';
   n225 <= '1';
   n226 <= '1';
   n227 <= '1';
   n228 <= '1';
   n229 <= '1';
   n230 <= '1';
   n231 <= '1';
   n232 <= '1';
   n233 <= '1';
   n234 <= '1';
   n235 <= '1';
   n236 <= '1';
   n237 <= '1';
   n238 <= '1';
   n239 <= '1';
   n240 <= '1';
   n241 <= '1';
   n242 <= '1';
   n243 <= '1';
   n244 <= '1';
   n245 <= '1';
   n246 <= '1';
   n247 <= '1';
   n248 <= '1';
   n249 <= '1';
   n250 <= '1';
   n251 <= '1';
   n252 <= '1';
   n253 <= '1';
   n254 <= '1';
   n255 <= '1';
   n256 <= '1';
   n257 <= '1';
   n258 <= '1';
   n259 <= '1';
   n260 <= '1';
   n261 <= '1';
   n262 <= '1';
   n263 <= '1';
   n264 <= '1';
   n265 <= '1';
   n266 <= '1';
   n267 <= '1';
   n268 <= '1';
   n269 <= '1';
   n270 <= '1';
   n271 <= '1';
   n272 <= '1';
   n273 <= '1';
   n274 <= '1';
   n275 <= '1';
   n276 <= '1';
   n277 <= '1';
   n278 <= '1';
   n279 <= '1';
   n280 <= '1';
   n281 <= '1';
   n282 <= '1';
   n283 <= '1';
   n284 <= '1';
   n285 <= '1';
   n286_port <= '1';
   add_592 : MEMORY_CONTROLLER_DW01_inc_0 port map( A(11) => IN1addr_11_port, 
                           A(10) => IN1addr_10_port, A(9) => IN1addr_9_port, 
                           A(8) => IN1addr_8_port, A(7) => IN1addr_7_port, A(6)
                           => IN1addr_6_port, A(5) => IN1addr_5_port, A(4) => 
                           IN1addr_4_port, A(3) => IN1addr_3_port, A(2) => 
                           IN1addr_2_port, A(1) => IN1addr_1_port, A(0) => 
                           IN1addr_0_port, SUM(11) => N999, SUM(10) => N998, 
                           SUM(9) => N997, SUM(8) => N996, SUM(7) => N995, 
                           SUM(6) => N994, SUM(5) => N993, SUM(4) => N992, 
                           SUM(3) => N991, SUM(2) => N990, SUM(1) => N989, 
                           SUM(0) => N988);
   add_589 : MEMORY_CONTROLLER_DW01_inc_1 port map( A(11) => RIRB1addr_11_port,
                           A(10) => RIRB1addr_10_port, A(9) => RIRB1addr_9_port
                           , A(8) => RIRB1addr_8_port, A(7) => RIRB1addr_7_port
                           , A(6) => RIRB1addr_6_port, A(5) => RIRB1addr_5_port
                           , A(4) => RIRB1addr_4_port, A(3) => RIRB1addr_3_port
                           , A(2) => RIRB1addr_2_port, A(1) => RIRB1addr_1_port
                           , A(0) => RIRB1addr_0_port, SUM(11) => N982, SUM(10)
                           => N981, SUM(9) => N980, SUM(8) => N979, SUM(7) => 
                           N978, SUM(6) => N977, SUM(5) => N976, SUM(4) => N975
                           , SUM(3) => N974, SUM(2) => N973, SUM(1) => N972, 
                           SUM(0) => N971);
   add_519 : MEMORY_CONTROLLER_DW01_inc_2 port map( A(11) => IN0addr_11_port, 
                           A(10) => IN0addr_10_port, A(9) => IN0addr_9_port, 
                           A(8) => IN0addr_8_port, A(7) => IN0addr_7_port, A(6)
                           => IN0addr_6_port, A(5) => IN0addr_5_port, A(4) => 
                           IN0addr_4_port, A(3) => IN0addr_3_port, A(2) => 
                           IN0addr_2_port, A(1) => IN0addr_1_port, A(0) => 
                           IN0addr_0_port, SUM(11) => N762, SUM(10) => N761, 
                           SUM(9) => N760, SUM(8) => N759, SUM(7) => N758, 
                           SUM(6) => N757, SUM(5) => N756, SUM(4) => N755, 
                           SUM(3) => N754, SUM(2) => N753, SUM(1) => N752, 
                           SUM(0) => N751);
   add_516 : MEMORY_CONTROLLER_DW01_inc_3 port map( A(11) => RIRBaddr_11_port, 
                           A(10) => RIRBaddr_10_port, A(9) => RIRBaddr_9_port, 
                           A(8) => RIRBaddr_8_port, A(7) => RIRBaddr_7_port, 
                           A(6) => RIRBaddr_6_port, A(5) => RIRBaddr_5_port, 
                           A(4) => RIRBaddr_4_port, A(3) => RIRBaddr_3_port, 
                           A(2) => RIRBaddr_2_port, A(1) => RIRBaddr_1_port, 
                           A(0) => RIRBaddr_0_port, SUM(11) => N745, SUM(10) =>
                           N744, SUM(9) => N743, SUM(8) => N742, SUM(7) => N741
                           , SUM(6) => N740, SUM(5) => N739, SUM(4) => N738, 
                           SUM(3) => N737, SUM(2) => N736, SUM(1) => N735, 
                           SUM(0) => N734);
   add_423 : MEMORY_CONTROLLER_DW01_inc_4 port map( A(11) => CORBaddr_11_port, 
                           A(10) => CORBaddr_10_port, A(9) => CORBaddr_9_port, 
                           A(8) => CORBaddr_8_port, A(7) => CORBaddr_7_port, 
                           A(6) => CORBaddr_6_port, A(5) => CORBaddr_5_port, 
                           A(4) => CORBaddr_4_port, A(3) => CORBaddr_3_port, 
                           A(2) => CORBaddr_2_port, A(1) => CORBaddr_1_port, 
                           A(0) => CORBaddr_0_port, SUM(11) => N443, SUM(10) =>
                           N442, SUM(9) => N441, SUM(8) => N440, SUM(7) => N439
                           , SUM(6) => N438, SUM(5) => N437, SUM(4) => N436, 
                           SUM(3) => N435, SUM(2) => N434, SUM(1) => N433, 
                           SUM(0) => N432);
   add_420 : MEMORY_CONTROLLER_DW01_inc_5 port map( A(11) => OUT2addr_11_port, 
                           A(10) => OUT2addr_10_port, A(9) => OUT2addr_9_port, 
                           A(8) => OUT2addr_8_port, A(7) => OUT2addr_7_port, 
                           A(6) => OUT2addr_6_port, A(5) => OUT2addr_5_port, 
                           A(4) => OUT2addr_4_port, A(3) => OUT2addr_3_port, 
                           A(2) => OUT2addr_2_port, A(1) => OUT2addr_1_port, 
                           A(0) => OUT2addr_0_port, SUM(11) => N428, SUM(10) =>
                           N427, SUM(9) => N426, SUM(8) => N425, SUM(7) => N424
                           , SUM(6) => N423, SUM(5) => N422, SUM(4) => N421, 
                           SUM(3) => N420, SUM(2) => N419, SUM(1) => N418, 
                           SUM(0) => N417);
   add_417 : MEMORY_CONTROLLER_DW01_inc_6 port map( A(11) => OUTaddr_11_port, 
                           A(10) => OUTaddr_10_port, A(9) => OUTaddr_9_port, 
                           A(8) => OUTaddr_8_port, A(7) => OUTaddr_7_port, A(6)
                           => OUTaddr_6_port, A(5) => OUTaddr_5_port, A(4) => 
                           OUTaddr_4_port, A(3) => OUTaddr_3_port, A(2) => 
                           OUTaddr_2_port, A(1) => OUTaddr_1_port, A(0) => 
                           OUTaddr_0_port, SUM(11) => N411, SUM(10) => N410, 
                           SUM(9) => N409, SUM(8) => N408, SUM(7) => N407, 
                           SUM(6) => N406, SUM(5) => N405, SUM(4) => N404, 
                           SUM(3) => N403, SUM(2) => N402, SUM(1) => N401, 
                           SUM(0) => N400);
   r297 : MEMORY_CONTROLLER_DW01_inc_9 port map( A(6) => outByteCount_6_port, 
                           A(5) => outByteCount_5_port, A(4) => 
                           outByteCount_4_port, A(3) => outByteCount_3_port, 
                           A(2) => outByteCount_2_port, A(1) => 
                           outByteCount_1_port, A(0) => outByteCount_0_port, 
                           SUM(6) => N292, SUM(5) => N291, SUM(4) => N290, 
                           SUM(3) => N289, SUM(2) => N288, SUM(1) => N287, 
                           SUM(0) => N286);
   r317_U1_1_1 : HAX1 port map( A => IN1ByteCount_1_port, B => 
                           IN1ByteCount_0_port, YC => r317_carry_2_port, YS => 
                           N897);
   r317_U1_1_2 : HAX1 port map( A => IN1ByteCount_2_port, B => 
                           r317_carry_2_port, YC => r317_carry_3_port, YS => 
                           N898);
   r317_U1_1_3 : HAX1 port map( A => IN1ByteCount_3_port, B => 
                           r317_carry_3_port, YC => r317_carry_4_port, YS => 
                           N899);
   r317_U1_1_4 : HAX1 port map( A => IN1ByteCount_4_port, B => 
                           r317_carry_4_port, YC => r317_carry_5_port, YS => 
                           N900);
   r308_U1_1_1 : HAX1 port map( A => IN0ByteCount_1_port, B => 
                           IN0ByteCount_0_port, YC => r308_carry_2_port, YS => 
                           N660);
   r308_U1_1_2 : HAX1 port map( A => IN0ByteCount_2_port, B => 
                           r308_carry_2_port, YC => r308_carry_3_port, YS => 
                           N661);
   r308_U1_1_3 : HAX1 port map( A => IN0ByteCount_3_port, B => 
                           r308_carry_3_port, YC => r308_carry_4_port, YS => 
                           N662);
   r308_U1_1_4 : HAX1 port map( A => IN0ByteCount_4_port, B => 
                           r308_carry_4_port, YC => r308_carry_5_port, YS => 
                           N663);
   U35 : INVX4 port map( A => n81, Y => n82);
   U36 : INVX2 port map( A => n357, Y => n425_port);
   U37 : AND2X2 port map( A => n815, B => n813, Y => n1);
   U38 : OR2X2 port map( A => n491, B => n688_port, Y => n2);
   U39 : XOR2X1 port map( A => OUT2addr_11_port, B => n31, Y => n3);
   U40 : NOR2X1 port map( A => n418_port, B => n391, Y => n4);
   U41 : NOR2X1 port map( A => n655, B => n288_port, Y => n5);
   U42 : NOR2X1 port map( A => n655, B => n536, Y => n6);
   U43 : NOR2X1 port map( A => n737_port, B => n649, Y => n7);
   U44 : NOR2X1 port map( A => n779, B => n737_port, Y => n8);
   U45 : NOR2X1 port map( A => n391, B => n417_port, Y => n9);
   U46 : NOR2X1 port map( A => n737_port, B => n287_port, Y => n10);
   U47 : INVX2 port map( A => n288_port, Y => n299);
   U48 : XNOR2X1 port map( A => add_377_aco_carry_9_port, B => CORBaddr_9_port,
                           Y => n11);
   U49 : XOR2X1 port map( A => n61, B => CORBaddr_11_port, Y => n12);
   U50 : XOR2X1 port map( A => RIRBaddr_11_port, B => n62, Y => n13);
   U51 : OR2X2 port map( A => n357, B => n84, Y => n459);
   U52 : OR2X1 port map( A => n376, B => N1495, Y => n15);
   U53 : INVX2 port map( A => n14, Y => n87);
   U54 : INVX2 port map( A => n350, Y => n364);
   U55 : INVX2 port map( A => n535, Y => n550);
   U56 : OR2X2 port map( A => N867, B => n653, Y => n14);
   U57 : INVX2 port map( A => n15, Y => n80);
   U58 : INVX2 port map( A => n16, Y => n86);
   U59 : INVX2 port map( A => n17, Y => n85);
   U60 : INVX2 port map( A => n96, Y => n94);
   U61 : INVX2 port map( A => n439_port, Y => n81);
   U62 : INVX2 port map( A => N1495, Y => N630);
   U197 : INVX2 port map( A => n376, Y => n314);
   U198 : INVX4 port map( A => n2, Y => n88);
   U199 : BUFX2 port map( A => n99, Y => n95);
   U200 : INVX2 port map( A => n92, Y => n380);
   U201 : OR2X2 port map( A => n653, B => N1497, Y => n16);
   U202 : OR2X2 port map( A => n476, B => n450, Y => n17);
   U203 : BUFX2 port map( A => n444, Y => n83);
   U204 : INVX2 port map( A => n18, Y => n84);
   U205 : INVX2 port map( A => n676_port, Y => n510);
   U206 : BUFX2 port map( A => n99, Y => n96);
   U207 : BUFX2 port map( A => n99, Y => n97);
   U208 : INVX2 port map( A => n89, Y => n362);
   U209 : BUFX2 port map( A => n99, Y => n98);
   U210 : INVX2 port map( A => n816, Y => n508);
   U211 : INVX4 port map( A => n1, Y => n92);
   U212 : BUFX2 port map( A => n346, Y => n90);
   U213 : INVX2 port map( A => n722, Y => n99);
   U214 : OR2X2 port map( A => n437_port, B => N1497, Y => n18);
   U215 : BUFX2 port map( A => n346, Y => n91);
   U216 : BUFX2 port map( A => n346, Y => n89);
   U217 : BUFX2 port map( A => n103, Y => n116);
   U218 : BUFX2 port map( A => n104, Y => n117);
   U219 : BUFX2 port map( A => n103, Y => n115);
   U220 : BUFX2 port map( A => n103, Y => n114);
   U221 : BUFX2 port map( A => n102, Y => n113);
   U222 : BUFX2 port map( A => n102, Y => n112);
   U223 : BUFX2 port map( A => n102, Y => n111);
   U224 : BUFX2 port map( A => n101, Y => n109);
   U225 : BUFX2 port map( A => n101, Y => n108);
   U226 : BUFX2 port map( A => n100, Y => n107);
   U227 : BUFX2 port map( A => n101, Y => n110);
   U228 : BUFX2 port map( A => n100, Y => n105);
   U229 : BUFX2 port map( A => n100, Y => n106);
   U230 : BUFX2 port map( A => n104, Y => n118);
   U231 : XNOR2X1 port map( A => add_371_aco_carry_10_port, B => 
                           OUTaddr_10_port, Y => n19);
   U232 : XNOR2X1 port map( A => add_371_aco_carry_9_port, B => OUTaddr_9_port,
                           Y => n20);
   U233 : XOR2X1 port map( A => n74, B => OUTaddr_11_port, Y => n73);
   U234 : XNOR2X1 port map( A => add_374_aco_carry_9_port, B => OUT2addr_9_port
                           , Y => n21);
   U235 : XNOR2X1 port map( A => add_374_aco_carry_8_port, B => OUT2addr_8_port
                           , Y => n22);
   U236 : XNOR2X1 port map( A => add_374_aco_carry_6_port, B => OUT2addr_6_port
                           , Y => n23);
   U237 : XNOR2X1 port map( A => add_374_aco_carry_10_port, B => 
                           OUT2addr_10_port, Y => n24);
   U238 : XNOR2X1 port map( A => add_490_aco_carry_9_port, B => RIRBaddr_9_port
                           , Y => n25);
   U239 : XNOR2X1 port map( A => add_490_aco_carry_8_port, B => RIRBaddr_8_port
                           , Y => n26);
   U240 : XNOR2X1 port map( A => add_490_aco_carry_7_port, B => RIRBaddr_7_port
                           , Y => n27);
   U241 : XNOR2X1 port map( A => add_490_aco_carry_6_port, B => RIRBaddr_6_port
                           , Y => n28);
   U242 : XNOR2X1 port map( A => add_563_aco_carry_10_port, B => 
                           RIRB1addr_10_port, Y => n29);
   U243 : XNOR2X1 port map( A => add_371_aco_carry_8_port, B => OUTaddr_8_port,
                           Y => n30);
   U244 : BUFX2 port map( A => mainState_0_port, Y => n93);
   U245 : NAND2X1 port map( A => OUT2addr_10_port, B => 
                           add_374_aco_carry_10_port, Y => n31);
   U246 : XNOR2X1 port map( A => add_563_aco_carry_7_port, B => 
                           RIRB1addr_7_port, Y => n32);
   U247 : XNOR2X1 port map( A => add_563_aco_carry_4_port, B => 
                           RIRB1addr_4_port, Y => n33);
   U248 : XNOR2X1 port map( A => add_563_aco_carry_1_port, B => 
                           RIRB1addr_1_port, Y => n34);
   U249 : XNOR2X1 port map( A => add_566_aco_carry_9_port, B => IN1addr_9_port,
                           Y => n35);
   U250 : XNOR2X1 port map( A => add_566_aco_carry_6_port, B => IN1addr_6_port,
                           Y => n36);
   U251 : XNOR2X1 port map( A => N867, B => RIRB1addr_0_port, Y => n37);
   U252 : XNOR2X1 port map( A => add_493_aco_carry_9_port, B => IN0addr_9_port,
                           Y => n38);
   U253 : XNOR2X1 port map( A => add_493_aco_carry_8_port, B => IN0addr_8_port,
                           Y => n39);
   U254 : XNOR2X1 port map( A => add_563_aco_carry_9_port, B => 
                           RIRB1addr_9_port, Y => n40);
   U255 : XNOR2X1 port map( A => add_563_aco_carry_8_port, B => 
                           RIRB1addr_8_port, Y => n41);
   U256 : XNOR2X1 port map( A => add_563_aco_carry_5_port, B => 
                           RIRB1addr_5_port, Y => n42);
   U257 : XNOR2X1 port map( A => add_563_aco_carry_3_port, B => 
                           RIRB1addr_3_port, Y => n43);
   U258 : XNOR2X1 port map( A => add_566_aco_carry_7_port, B => IN1addr_7_port,
                           Y => n44);
   U259 : NOR2X1 port map( A => n45, B => n46, Y => add_490_aco_carry_7_port);
   U260 : NAND2X1 port map( A => add_490_aco_carry_4_port, B => RIRBaddr_4_port
                           , Y => n45);
   U261 : NAND2X1 port map( A => RIRBaddr_6_port, B => RIRBaddr_5_port, Y => 
                           n46);
   U262 : XNOR2X1 port map( A => add_371_aco_carry_7_port, B => OUTaddr_7_port,
                           Y => n47);
   U263 : XNOR2X1 port map( A => add_377_aco_carry_10_port, B => 
                           CORBaddr_10_port, Y => n48);
   U264 : XNOR2X1 port map( A => add_377_aco_carry_8_port, B => CORBaddr_8_port
                           , Y => n49);
   U265 : XNOR2X1 port map( A => add_377_aco_carry_7_port, B => CORBaddr_7_port
                           , Y => n50);
   U266 : XNOR2X1 port map( A => add_377_aco_carry_6_port, B => CORBaddr_6_port
                           , Y => n51);
   U267 : XNOR2X1 port map( A => add_377_aco_carry_5_port, B => CORBaddr_5_port
                           , Y => n52);
   U268 : XNOR2X1 port map( A => add_377_aco_carry_4_port, B => CORBaddr_4_port
                           , Y => n53);
   U269 : XNOR2X1 port map( A => add_377_aco_carry_3_port, B => CORBaddr_3_port
                           , Y => n54);
   U270 : XNOR2X1 port map( A => add_377_aco_carry_2_port, B => CORBaddr_2_port
                           , Y => n55);
   U271 : XNOR2X1 port map( A => add_377_aco_carry_1_port, B => CORBaddr_1_port
                           , Y => n56);
   U272 : XNOR2X1 port map( A => add_377_aco_B_0_port, B => CORBaddr_0_port, Y 
                           => n57);
   U273 : XNOR2X1 port map( A => add_566_aco_carry_10_port, B => 
                           IN1addr_10_port, Y => n58);
   U274 : XNOR2X1 port map( A => add_493_aco_carry_10_port, B => 
                           IN0addr_10_port, Y => n59);
   U275 : XNOR2X1 port map( A => add_490_aco_carry_10_port, B => 
                           RIRBaddr_10_port, Y => n60);
   U276 : NAND2X1 port map( A => CORBaddr_10_port, B => 
                           add_377_aco_carry_10_port, Y => n61);
   U277 : NAND2X1 port map( A => add_490_aco_carry_9_port, B => n76, Y => n62);
   U278 : INVX2 port map( A => IN1addr_11_port, Y => n66);
   U279 : INVX2 port map( A => RIRB1addr_11_port, Y => n78);
   U280 : BUFX2 port map( A => RST, Y => n102);
   U281 : BUFX2 port map( A => RST, Y => n103);
   U282 : BUFX2 port map( A => RST, Y => n101);
   U283 : BUFX2 port map( A => RST, Y => n100);
   U284 : BUFX2 port map( A => RST, Y => n104);
   U285 : AND2X2 port map( A => IN0addr_1_port, B => add_493_aco_carry_1_port, 
                           Y => add_493_aco_carry_2_port);
   U286 : AND2X2 port map( A => n504, B => n120, Y => n63);
   U287 : INVX2 port map( A => n63, Y => n794);
   U288 : AND2X2 port map( A => OUT2addr_2_port, B => add_374_aco_carry_2_port,
                           Y => add_374_aco_carry_3_port);
   U289 : INVX2 port map( A => mainState_2_port, Y => n821);
   U290 : AND2X2 port map( A => CORBaddr_8_port, B => CORBaddr_9_port, Y => n64
                           );
   U291 : XNOR2X1 port map( A => n67, B => n66, Y => n65);
   U292 : NAND2X1 port map( A => IN1addr_10_port, B => 
                           add_566_aco_carry_10_port, Y => n67);
   U293 : AND2X2 port map( A => OUTaddr_1_port, B => OUTaddr_2_port, Y => n68);
   U294 : AND2X2 port map( A => OUTaddr_7_port, B => OUTaddr_8_port, Y => n69);
   U295 : XNOR2X1 port map( A => n71, B => n651, Y => n70);
   U296 : NAND2X1 port map( A => IN0addr_10_port, B => 
                           add_493_aco_carry_10_port, Y => n71);
   U297 : OR2X1 port map( A => outByteCount_3_port, B => outByteCount_4_port, Y
                           => n824);
   U298 : INVX1 port map( A => outByteCount_4_port, Y => n717);
   U299 : AND2X2 port map( A => RIRB1addr_6_port, B => RIRB1addr_7_port, Y => 
                           n72);
   U300 : AND2X2 port map( A => OUT2addr_0_port, B => N1499, Y => 
                           add_374_aco_carry_1_port);
   U301 : AND2X2 port map( A => RIRB1addr_0_port, B => N867, Y => 
                           add_563_aco_carry_1_port);
   U302 : INVX2 port map( A => N1497, Y => N867);
   U303 : OR2X2 port map( A => n299, B => n95, Y => n492);
   U304 : AND2X2 port map( A => IN0addr_2_port, B => add_493_aco_carry_2_port, 
                           Y => add_493_aco_carry_3_port);
   U305 : AND2X2 port map( A => IN1addr_2_port, B => add_566_aco_carry_2_port, 
                           Y => add_566_aco_carry_3_port);
   U306 : AND2X2 port map( A => CORBaddr_2_port, B => add_377_aco_carry_2_port,
                           Y => add_377_aco_carry_3_port);
   U307 : AND2X2 port map( A => CORBaddr_1_port, B => add_377_aco_carry_1_port,
                           Y => add_377_aco_carry_2_port);
   U308 : NAND2X1 port map( A => OUTaddr_10_port, B => 
                           add_371_aco_carry_10_port, Y => n74);
   U309 : AND2X2 port map( A => OUT2addr_1_port, B => add_374_aco_carry_1_port,
                           Y => add_374_aco_carry_2_port);
   U310 : AND2X2 port map( A => n807, B => mainState_3_port, Y => n815);
   U311 : INVX2 port map( A => n741_port, Y => n760_port);
   U312 : AND2X2 port map( A => CORBaddr_3_port, B => add_377_aco_carry_3_port,
                           Y => add_377_aco_carry_4_port);
   U313 : AND2X2 port map( A => OUTaddr_9_port, B => add_371_aco_carry_9_port, 
                           Y => add_371_aco_carry_10_port);
   U314 : INVX2 port map( A => mainState_3_port, Y => n684_port);
   U315 : AND2X2 port map( A => n810, B => n684_port, Y => n812);
   U316 : INVX2 port map( A => outByteCount_5_port, Y => n75);
   U317 : AND2X2 port map( A => RIRB1addr_2_port, B => add_563_aco_carry_2_port
                           , Y => add_563_aco_carry_3_port);
   U318 : AND2X2 port map( A => RIRB1addr_1_port, B => add_563_aco_carry_1_port
                           , Y => add_563_aco_carry_2_port);
   U319 : AND2X2 port map( A => OUT2addr_4_port, B => add_374_aco_carry_4_port,
                           Y => add_374_aco_carry_5_port);
   U320 : AND2X2 port map( A => OUT2addr_3_port, B => add_374_aco_carry_3_port,
                           Y => add_374_aco_carry_4_port);
   U321 : AND2X2 port map( A => IN1addr_4_port, B => add_566_aco_carry_4_port, 
                           Y => add_566_aco_carry_5_port);
   U322 : AND2X2 port map( A => IN1addr_3_port, B => add_566_aco_carry_3_port, 
                           Y => add_566_aco_carry_4_port);
   U323 : AND2X2 port map( A => RIRBaddr_9_port, B => RIRBaddr_10_port, Y => 
                           n76);
   U324 : XNOR2X1 port map( A => n79, B => n78, Y => n77);
   U325 : NAND2X1 port map( A => RIRB1addr_10_port, B => 
                           add_563_aco_carry_10_port, Y => n79);
   U326 : AND2X2 port map( A => CORBaddr_4_port, B => add_377_aco_carry_4_port,
                           Y => add_377_aco_carry_5_port);
   U327 : AND2X2 port map( A => IN0addr_5_port, B => add_493_aco_carry_5_port, 
                           Y => add_493_aco_carry_6_port);
   U328 : AND2X2 port map( A => IN0addr_4_port, B => add_493_aco_carry_4_port, 
                           Y => add_493_aco_carry_5_port);
   U329 : AND2X2 port map( A => IN0addr_3_port, B => add_493_aco_carry_3_port, 
                           Y => add_493_aco_carry_4_port);
   U330 : AND2X2 port map( A => RIRBaddr_3_port, B => add_490_aco_carry_3_port,
                           Y => add_490_aco_carry_4_port);
   U331 : AND2X2 port map( A => OUT2addr_7_port, B => add_374_aco_carry_7_port,
                           Y => add_374_aco_carry_8_port);
   U332 : AND2X2 port map( A => OUT2addr_6_port, B => add_374_aco_carry_6_port,
                           Y => add_374_aco_carry_7_port);
   U333 : AND2X2 port map( A => OUT2addr_5_port, B => add_374_aco_carry_5_port,
                           Y => add_374_aco_carry_6_port);
   U334 : INVX2 port map( A => outByteCount_3_port, Y => n715);
   U335 : AND2X2 port map( A => OUTaddr_1_port, B => add_371_aco_carry_1_port, 
                           Y => add_371_aco_carry_2_port);
   U336 : AND2X2 port map( A => add_371_aco_carry_1_port, B => n68, Y => 
                           add_371_aco_carry_3_port);
   U337 : AND2X2 port map( A => OUTaddr_3_port, B => add_371_aco_carry_3_port, 
                           Y => add_371_aco_carry_4_port);
   U338 : AND2X2 port map( A => OUTaddr_4_port, B => add_371_aco_carry_4_port, 
                           Y => add_371_aco_carry_5_port);
   U339 : AND2X2 port map( A => RIRB1addr_8_port, B => add_563_aco_carry_8_port
                           , Y => add_563_aco_carry_9_port);
   U340 : AND2X2 port map( A => RIRB1addr_9_port, B => add_563_aco_carry_9_port
                           , Y => add_563_aco_carry_10_port);
   U341 : AND2X2 port map( A => IN1addr_8_port, B => add_566_aco_carry_8_port, 
                           Y => add_566_aco_carry_9_port);
   U342 : AND2X2 port map( A => IN1addr_7_port, B => add_566_aco_carry_7_port, 
                           Y => add_566_aco_carry_8_port);
   U343 : AND2X2 port map( A => IN1addr_9_port, B => add_566_aco_carry_9_port, 
                           Y => add_566_aco_carry_10_port);
   U344 : AND2X2 port map( A => add_490_aco_carry_7_port, B => RIRBaddr_7_port,
                           Y => add_490_aco_carry_8_port);
   U345 : AND2X2 port map( A => CORBaddr_7_port, B => add_377_aco_carry_7_port,
                           Y => add_377_aco_carry_8_port);
   U346 : AND2X2 port map( A => CORBaddr_6_port, B => add_377_aco_carry_6_port,
                           Y => add_377_aco_carry_7_port);
   U347 : AND2X2 port map( A => CORBaddr_5_port, B => add_377_aco_carry_5_port,
                           Y => add_377_aco_carry_6_port);
   U348 : INVX2 port map( A => n790, Y => n738_port);
   U349 : AND2X2 port map( A => RIRB1addr_6_port, B => add_563_aco_carry_6_port
                           , Y => add_563_aco_carry_7_port);
   U350 : AND2X2 port map( A => add_563_aco_carry_6_port, B => n72, Y => 
                           add_563_aco_carry_8_port);
   U351 : AND2X2 port map( A => OUT2addr_9_port, B => add_374_aco_carry_9_port,
                           Y => add_374_aco_carry_10_port);
   U352 : AND2X2 port map( A => OUT2addr_8_port, B => add_374_aco_carry_8_port,
                           Y => add_374_aco_carry_9_port);
   U353 : AND2X2 port map( A => OUTaddr_5_port, B => add_371_aco_carry_5_port, 
                           Y => add_371_aco_carry_6_port);
   U354 : AND2X2 port map( A => OUTaddr_0_port, B => add_371_aco_B_0_port, Y =>
                           add_371_aco_carry_1_port);
   U355 : AND2X2 port map( A => IN0addr_7_port, B => add_493_aco_carry_7_port, 
                           Y => add_493_aco_carry_8_port);
   U356 : AND2X2 port map( A => IN0addr_6_port, B => add_493_aco_carry_6_port, 
                           Y => add_493_aco_carry_7_port);
   U357 : AND2X2 port map( A => IN0addr_9_port, B => add_493_aco_carry_9_port, 
                           Y => add_493_aco_carry_10_port);
   U358 : AND2X2 port map( A => IN0addr_8_port, B => add_493_aco_carry_8_port, 
                           Y => add_493_aco_carry_9_port);
   U359 : AND2X2 port map( A => IN1addr_6_port, B => add_566_aco_carry_6_port, 
                           Y => add_566_aco_carry_7_port);
   U360 : AND2X2 port map( A => IN1addr_5_port, B => add_566_aco_carry_5_port, 
                           Y => add_566_aco_carry_6_port);
   U361 : AND2X2 port map( A => add_377_aco_carry_8_port, B => n64, Y => 
                           add_377_aco_carry_10_port);
   U362 : AND2X2 port map( A => CORBaddr_8_port, B => add_377_aco_carry_8_port,
                           Y => add_377_aco_carry_9_port);
   U363 : INVX2 port map( A => n649, Y => add_377_aco_B_0_port);
   U364 : AND2X2 port map( A => OUTaddr_7_port, B => add_371_aco_carry_7_port, 
                           Y => add_371_aco_carry_8_port);
   U365 : AND2X2 port map( A => OUTaddr_6_port, B => add_371_aco_carry_6_port, 
                           Y => add_371_aco_carry_7_port);
   U366 : AND2X2 port map( A => add_371_aco_carry_7_port, B => n69, Y => 
                           add_371_aco_carry_9_port);
   U367 : AND2X2 port map( A => RIRBaddr_5_port, B => add_490_aco_carry_5_port,
                           Y => add_490_aco_carry_6_port);
   U368 : AND2X2 port map( A => RIRBaddr_4_port, B => add_490_aco_carry_4_port,
                           Y => add_490_aco_carry_5_port);
   U369 : AND2X2 port map( A => RIRBaddr_9_port, B => add_490_aco_carry_9_port,
                           Y => add_490_aco_carry_10_port);
   U370 : AND2X2 port map( A => RIRBaddr_8_port, B => add_490_aco_carry_8_port,
                           Y => add_490_aco_carry_9_port);
   U371 : INVX2 port map( A => n828, Y => n827);
   U372 : AND2X2 port map( A => RIRB1addr_4_port, B => add_563_aco_carry_4_port
                           , Y => add_563_aco_carry_5_port);
   U373 : AND2X2 port map( A => RIRB1addr_3_port, B => add_563_aco_carry_3_port
                           , Y => add_563_aco_carry_4_port);
   U374 : AND2X2 port map( A => RIRB1addr_5_port, B => add_563_aco_carry_5_port
                           , Y => add_563_aco_carry_6_port);
   U375 : INVX2 port map( A => n826, Y => n825);
   U376 : AND2X2 port map( A => n807, B => n812, Y => n509);
   U377 : XOR2X1 port map( A => add_566_aco_carry_8_port, B => IN1addr_8_port, 
                           Y => N929);
   U378 : XOR2X1 port map( A => add_566_aco_carry_5_port, B => IN1addr_5_port, 
                           Y => N926);
   U379 : XOR2X1 port map( A => add_566_aco_carry_4_port, B => IN1addr_4_port, 
                           Y => N925);
   U380 : XOR2X1 port map( A => add_566_aco_carry_3_port, B => IN1addr_3_port, 
                           Y => N924);
   U381 : XOR2X1 port map( A => add_566_aco_carry_2_port, B => IN1addr_2_port, 
                           Y => N923);
   U382 : AND2X1 port map( A => IN1addr_1_port, B => add_566_aco_carry_1_port, 
                           Y => add_566_aco_carry_2_port);
   U383 : XOR2X1 port map( A => add_566_aco_carry_1_port, B => IN1addr_1_port, 
                           Y => N922);
   U384 : AND2X1 port map( A => IN1addr_0_port, B => N1497, Y => 
                           add_566_aco_carry_1_port);
   U385 : XOR2X1 port map( A => N1497, B => IN1addr_0_port, Y => N921);
   U386 : XOR2X1 port map( A => add_563_aco_carry_6_port, B => RIRB1addr_6_port
                           , Y => N915);
   U387 : XOR2X1 port map( A => add_563_aco_carry_2_port, B => RIRB1addr_2_port
                           , Y => N911);
   U388 : XOR2X1 port map( A => add_371_aco_carry_6_port, B => OUTaddr_6_port, 
                           Y => N312);
   U389 : XOR2X1 port map( A => add_371_aco_carry_5_port, B => OUTaddr_5_port, 
                           Y => N311);
   U390 : XOR2X1 port map( A => add_371_aco_carry_4_port, B => OUTaddr_4_port, 
                           Y => N310);
   U391 : XOR2X1 port map( A => add_371_aco_carry_3_port, B => OUTaddr_3_port, 
                           Y => N309);
   U392 : XOR2X1 port map( A => add_371_aco_carry_2_port, B => OUTaddr_2_port, 
                           Y => N308);
   U393 : XOR2X1 port map( A => add_371_aco_carry_1_port, B => OUTaddr_1_port, 
                           Y => N307);
   U394 : XOR2X1 port map( A => add_371_aco_B_0_port, B => OUTaddr_0_port, Y =>
                           N306);
   U395 : XOR2X1 port map( A => add_374_aco_carry_7_port, B => OUT2addr_7_port,
                           Y => N337);
   U396 : XOR2X1 port map( A => add_374_aco_carry_5_port, B => OUT2addr_5_port,
                           Y => N335);
   U397 : XOR2X1 port map( A => add_374_aco_carry_4_port, B => OUT2addr_4_port,
                           Y => N334);
   U398 : XOR2X1 port map( A => add_374_aco_carry_3_port, B => OUT2addr_3_port,
                           Y => N333);
   U399 : XOR2X1 port map( A => add_374_aco_carry_2_port, B => OUT2addr_2_port,
                           Y => N332);
   U400 : XOR2X1 port map( A => add_374_aco_carry_1_port, B => OUT2addr_1_port,
                           Y => N331);
   U401 : XOR2X1 port map( A => N1499, B => OUT2addr_0_port, Y => N330);
   U402 : AND2X1 port map( A => CORBaddr_0_port, B => add_377_aco_B_0_port, Y 
                           => add_377_aco_carry_1_port);
   U403 : XOR2X1 port map( A => add_493_aco_carry_7_port, B => IN0addr_7_port, 
                           Y => N691);
   U404 : XOR2X1 port map( A => add_493_aco_carry_6_port, B => IN0addr_6_port, 
                           Y => N690);
   U405 : XOR2X1 port map( A => add_493_aco_carry_5_port, B => IN0addr_5_port, 
                           Y => N689);
   U406 : XOR2X1 port map( A => add_493_aco_carry_4_port, B => IN0addr_4_port, 
                           Y => N688);
   U407 : XOR2X1 port map( A => add_493_aco_carry_3_port, B => IN0addr_3_port, 
                           Y => N687);
   U408 : XOR2X1 port map( A => add_493_aco_carry_2_port, B => IN0addr_2_port, 
                           Y => N686);
   U409 : XOR2X1 port map( A => add_493_aco_carry_1_port, B => IN0addr_1_port, 
                           Y => N685);
   U410 : AND2X1 port map( A => IN0addr_0_port, B => N1495, Y => 
                           add_493_aco_carry_1_port);
   U411 : XOR2X1 port map( A => N1495, B => IN0addr_0_port, Y => N684);
   U412 : XOR2X1 port map( A => add_490_aco_carry_5_port, B => RIRBaddr_5_port,
                           Y => N677);
   U413 : XOR2X1 port map( A => add_490_aco_carry_4_port, B => RIRBaddr_4_port,
                           Y => N676);
   U414 : XOR2X1 port map( A => add_490_aco_carry_3_port, B => RIRBaddr_3_port,
                           Y => N675);
   U415 : AND2X1 port map( A => RIRBaddr_2_port, B => add_490_aco_carry_2_port,
                           Y => add_490_aco_carry_3_port);
   U416 : XOR2X1 port map( A => add_490_aco_carry_2_port, B => RIRBaddr_2_port,
                           Y => N674);
   U417 : AND2X1 port map( A => RIRBaddr_1_port, B => add_490_aco_carry_1_port,
                           Y => add_490_aco_carry_2_port);
   U418 : XOR2X1 port map( A => add_490_aco_carry_1_port, B => RIRBaddr_1_port,
                           Y => N673);
   U419 : AND2X1 port map( A => RIRBaddr_0_port, B => N630, Y => 
                           add_490_aco_carry_1_port);
   U420 : XOR2X1 port map( A => N630, B => RIRBaddr_0_port, Y => N672);
   U421 : XOR2X1 port map( A => r308_carry_5_port, B => IN0ByteCount_5_port, Y 
                           => N664);
   U422 : XOR2X1 port map( A => r317_carry_5_port, B => IN1ByteCount_5_port, Y 
                           => N901);
   U423 : NAND2X1 port map( A => n119, B => n120, Y => nextRW_i);
   U424 : OAI21X1 port map( A => n287_port, B => n288_port, C => n289_port, Y 
                           => nextOUThold);
   U425 : NAND2X1 port map( A => n290_port, B => OUThold, Y => n289_port);
   U426 : AOI21X1 port map( A => SYNCcount_2_port, B => SYNCcount_1_port, C => 
                           SYNCcount_3_port, Y => n290_port);
   U427 : NOR2X1 port map( A => n291_port, B => n292_port, Y => 
                           nextMiniOUTstate_1_port);
   U428 : NAND2X1 port map( A => n293, B => n294, Y => n292_port);
   U429 : INVX1 port map( A => REQ_Tx_DATA_port, Y => n291_port);
   U430 : OAI21X1 port map( A => n295, B => n296, C => n297, Y => 
                           nextMiniOUTstate_0_port);
   U431 : NAND3X1 port map( A => n298, B => n294, C => REQ_Tx_DATA_port, Y => 
                           n297);
   U432 : INVX1 port map( A => Tx_DATA_STB, Y => n294);
   U433 : NAND2X1 port map( A => n299, B => n300, Y => n296);
   U434 : OR2X1 port map( A => miniOUTstate_0_port, B => miniOUTstate_1_port, Y
                           => n295);
   U435 : NOR2X1 port map( A => n301, B => n302, Y => nextMiniINstate_1_port);
   U436 : NAND2X1 port map( A => n303, B => n304, Y => n302);
   U437 : OAI21X1 port map( A => n303, B => n305, C => n306_port, Y => 
                           nextMiniINstate_0_port);
   U438 : NAND3X1 port map( A => n307_port, B => n308_port, C => n309_port, Y 
                           => n306_port);
   U439 : OAI22X1 port map( A => n310_port, B => n311_port, C => n312_port, D 
                           => n313, Y => n309_port);
   U440 : NAND3X1 port map( A => n314, B => n315, C => n316, Y => n313);
   U441 : INVX1 port map( A => n317, Y => n315);
   U442 : NAND3X1 port map( A => n318, B => n319, C => n320, Y => n312_port);
   U443 : NAND3X1 port map( A => n321, B => n322, C => n323, Y => n311_port);
   U444 : INVX1 port map( A => n324, Y => n322);
   U445 : NAND3X1 port map( A => n325, B => n326, C => n327, Y => n310_port);
   U446 : INVX1 port map( A => miniINstate_0_port, Y => n307_port);
   U447 : NAND2X1 port map( A => NEW_Rx_DATA_port, B => n304, Y => n305);
   U448 : INVX1 port map( A => Rx_DATA_STB, Y => n304);
   U449 : OAI21X1 port map( A => n328, B => n329, C => n330_port, Y => 
                           nextBUSY_i);
   U450 : INVX1 port map( A => n330_port, Y => n831);
   U451 : NOR2X1 port map( A => n331_port, B => n332_port, Y => n330_port);
   U452 : OAI21X1 port map( A => n328, B => n333_port, C => n334_port, Y => 
                           n332_port);
   U453 : INVX1 port map( A => n335_port, Y => n328);
   U454 : OAI21X1 port map( A => n336, B => n337_port, C => n338, Y => 
                           n331_port);
   U455 : AND2X1 port map( A => n339, B => n120, Y => n338);
   U456 : INVX1 port map( A => n340, Y => n336);
   U457 : INVX1 port map( A => n341, Y => n832);
   U458 : OAI22X1 port map( A => EN_port, B => n342, C => n343, D => n344, Y =>
                           n341);
   U459 : NAND3X1 port map( A => n334_port, B => n329, C => n337_port, Y => 
                           n344);
   U460 : INVX1 port map( A => n345, Y => n334_port);
   U461 : NAND3X1 port map( A => n92, B => n91, C => n347, Y => n345);
   U462 : NAND3X1 port map( A => n333_port, B => n339, C => n120, Y => n343);
   U463 : INVX1 port map( A => n348, Y => n833);
   U464 : INVX1 port map( A => n349, Y => CRIT);
   U465 : INVX1 port map( A => n301, Y => NEW_Rx_DATA_port);
   U466 : NAND2X1 port map( A => miniINstate_0_port, B => n308_port, Y => n301)
                           ;
   U467 : INVX1 port map( A => miniINstate_1_port, Y => n308_port);
   U468 : XOR2X1 port map( A => I0wait_1_port, B => n1000, Y => n999_port);
   U469 : OAI21X1 port map( A => n350, B => n351, C => n352, Y => n998_port);
   U470 : OAI21X1 port map( A => I0wait_1_port, B => n353, C => N1113, Y => 
                           n352);
   U471 : INVX1 port map( A => n1000, Y => n353);
   U472 : NAND2X1 port map( A => n354, B => n92, Y => n351);
   U473 : INVX1 port map( A => n355, Y => n997_port);
   U474 : XOR2X1 port map( A => n356, B => n355, Y => n996_port);
   U475 : OAI21X1 port map( A => n357, B => n358, C => n359, Y => n995_port);
   U476 : OAI21X1 port map( A => I1wait_1_port, B => n355, C => N1124, Y => 
                           n359);
   U477 : NAND2X1 port map( A => n360, B => n361, Y => n355);
   U478 : OAI21X1 port map( A => n362, B => n357, C => n363, Y => n360);
   U479 : NAND2X1 port map( A => n363, B => n90, Y => n358);
   U480 : OAI21X1 port map( A => n364, B => n365, C => n366, Y => n994_port);
   U481 : NAND2X1 port map( A => n365, B => n367, Y => n366);
   U482 : INVX1 port map( A => IN0ByteCount_0_port, Y => n365);
   U483 : OAI21X1 port map( A => n364, B => n368, C => n369, Y => n993_port);
   U484 : NAND2X1 port map( A => N660, B => n367, Y => n369);
   U485 : INVX1 port map( A => IN0ByteCount_1_port, Y => n368);
   U486 : OAI21X1 port map( A => n364, B => n370, C => n371, Y => n992_port);
   U487 : NAND2X1 port map( A => N661, B => n367, Y => n371);
   U488 : OAI21X1 port map( A => n364, B => n372, C => n373, Y => n991_port);
   U489 : NAND2X1 port map( A => N662, B => n367, Y => n373);
   U490 : OAI21X1 port map( A => n364, B => n325, C => n374, Y => n990_port);
   U491 : NAND2X1 port map( A => N663, B => n367, Y => n374);
   U492 : OAI21X1 port map( A => n364, B => n326, C => n375, Y => n989_port);
   U493 : NAND2X1 port map( A => N664, B => n367, Y => n375);
   U494 : OAI21X1 port map( A => n316, B => n376, C => n92, Y => n367);
   U495 : NAND2X1 port map( A => n377, B => n378, Y => n988_port);
   U496 : AOI21X1 port map( A => RIRBaddr_0_port, B => n379, C => n9, Y => n378
                           );
   U497 : AOI22X1 port map( A => N734, B => n80, C => N672, D => n380, Y => 
                           n377);
   U498 : NAND2X1 port map( A => n381, B => n382, Y => n987);
   U499 : AOI21X1 port map( A => RIRBaddr_1_port, B => n379, C => n9, Y => n382
                           );
   U500 : AOI22X1 port map( A => N735, B => n80, C => N673, D => n380, Y => 
                           n381);
   U501 : NAND2X1 port map( A => n383, B => n384, Y => n986);
   U502 : AOI21X1 port map( A => RIRBaddr_2_port, B => n379, C => n9, Y => n384
                           );
   U503 : AOI22X1 port map( A => N736, B => n80, C => N674, D => n380, Y => 
                           n383);
   U504 : NAND2X1 port map( A => n385, B => n386, Y => n985);
   U505 : AOI21X1 port map( A => RIRBaddr_3_port, B => n379, C => n9, Y => n386
                           );
   U506 : AOI22X1 port map( A => N737, B => n80, C => N675, D => n380, Y => 
                           n385);
   U507 : NAND2X1 port map( A => n387, B => n388, Y => n984);
   U508 : AOI21X1 port map( A => RIRBaddr_4_port, B => n379, C => n9, Y => n388
                           );
   U509 : AOI22X1 port map( A => N738, B => n80, C => N676, D => n380, Y => 
                           n387);
   U510 : NAND2X1 port map( A => n389, B => n390, Y => n983);
   U511 : AOI21X1 port map( A => RIRBaddr_5_port, B => n379, C => n9, Y => n390
                           );
   U512 : NAND2X1 port map( A => n364, B => n391, Y => n379);
   U513 : AOI22X1 port map( A => N739, B => n80, C => N677, D => n380, Y => 
                           n389);
   U514 : OAI21X1 port map( A => n92, B => n28, C => n392, Y => n982_port);
   U515 : AOI22X1 port map( A => RIRBaddr_6_port, B => n393, C => N740, D => 
                           n80, Y => n392);
   U516 : OAI21X1 port map( A => n92, B => n27, C => n394, Y => n981_port);
   U517 : AOI22X1 port map( A => RIRBaddr_7_port, B => n393, C => N741, D => 
                           n80, Y => n394);
   U518 : OAI21X1 port map( A => n92, B => n26, C => n395, Y => n980_port);
   U519 : AOI22X1 port map( A => RIRBaddr_8_port, B => n393, C => N742, D => 
                           n80, Y => n395);
   U520 : OAI21X1 port map( A => n92, B => n25, C => n396, Y => n979_port);
   U521 : AOI22X1 port map( A => RIRBaddr_9_port, B => n393, C => N743, D => 
                           n80, Y => n396);
   U522 : OAI21X1 port map( A => n92, B => n60, C => n397, Y => n978_port);
   U523 : AOI22X1 port map( A => RIRBaddr_10_port, B => n393, C => N744, D => 
                           n80, Y => n397);
   U524 : OAI21X1 port map( A => n92, B => n13, C => n398, Y => n977_port);
   U525 : AOI22X1 port map( A => RIRBaddr_11_port, B => n393, C => N745, D => 
                           n80, Y => n398);
   U526 : OAI21X1 port map( A => n316, B => n391, C => n364, Y => n393);
   U527 : INVX1 port map( A => n399, Y => n316);
   U528 : NAND2X1 port map( A => n400_port, B => n401_port, Y => n976_port);
   U529 : AOI21X1 port map( A => IN0addr_0_port, B => n402_port, C => n9, Y => 
                           n401_port);
   U530 : AOI22X1 port map( A => N751, B => n4, C => N684, D => n380, Y => 
                           n400_port);
   U531 : NAND2X1 port map( A => n403_port, B => n404_port, Y => n975_port);
   U532 : AOI21X1 port map( A => IN0addr_1_port, B => n402_port, C => n9, Y => 
                           n404_port);
   U533 : AOI22X1 port map( A => N752, B => n4, C => N685, D => n380, Y => 
                           n403_port);
   U534 : NAND2X1 port map( A => n405_port, B => n406_port, Y => n974_port);
   U535 : AOI21X1 port map( A => IN0addr_2_port, B => n402_port, C => n9, Y => 
                           n406_port);
   U536 : AOI22X1 port map( A => N753, B => n4, C => N686, D => n380, Y => 
                           n405_port);
   U537 : NAND2X1 port map( A => n407_port, B => n408_port, Y => n973_port);
   U538 : AOI21X1 port map( A => IN0addr_3_port, B => n402_port, C => n9, Y => 
                           n408_port);
   U539 : AOI22X1 port map( A => N754, B => n4, C => N687, D => n380, Y => 
                           n407_port);
   U540 : NAND2X1 port map( A => n409_port, B => n410_port, Y => n972_port);
   U541 : AOI21X1 port map( A => IN0addr_4_port, B => n402_port, C => n9, Y => 
                           n410_port);
   U542 : AOI22X1 port map( A => N755, B => n4, C => N688, D => n380, Y => 
                           n409_port);
   U543 : NAND2X1 port map( A => n411_port, B => n412, Y => n971_port);
   U544 : AOI21X1 port map( A => IN0addr_5_port, B => n402_port, C => n9, Y => 
                           n412);
   U545 : AOI22X1 port map( A => N756, B => n4, C => N689, D => n380, Y => 
                           n411_port);
   U546 : NAND2X1 port map( A => n413, B => n414, Y => n970);
   U547 : AOI21X1 port map( A => IN0addr_6_port, B => n402_port, C => n9, Y => 
                           n414);
   U548 : AOI22X1 port map( A => N757, B => n4, C => N690, D => n380, Y => n413
                           );
   U549 : NAND2X1 port map( A => n415, B => n416, Y => n969);
   U550 : AOI21X1 port map( A => IN0addr_7_port, B => n402_port, C => n9, Y => 
                           n416);
   U551 : INVX1 port map( A => n418_port, Y => n417_port);
   U552 : OR2X1 port map( A => n350, B => n80, Y => n402_port);
   U553 : AOI22X1 port map( A => N758, B => n4, C => N691, D => n380, Y => n415
                           );
   U554 : OAI21X1 port map( A => n92, B => n39, C => n419_port, Y => n968);
   U555 : AOI22X1 port map( A => IN0addr_8_port, B => n420_port, C => N759, D 
                           => n4, Y => n419_port);
   U556 : OAI21X1 port map( A => n92, B => n38, C => n421_port, Y => n967);
   U557 : AOI22X1 port map( A => IN0addr_9_port, B => n420_port, C => N760, D 
                           => n4, Y => n421_port);
   U558 : OAI21X1 port map( A => n92, B => n59, C => n422_port, Y => n966);
   U559 : AOI22X1 port map( A => IN0addr_10_port, B => n420_port, C => N761, D 
                           => n4, Y => n422_port);
   U560 : OAI21X1 port map( A => n70, B => n92, C => n423_port, Y => n965);
   U561 : AOI22X1 port map( A => IN0addr_11_port, B => n420_port, C => N762, D 
                           => n4, Y => n423_port);
   U562 : NAND2X1 port map( A => n314, B => N1495, Y => n391);
   U563 : OAI21X1 port map( A => n376, B => n424_port, C => n364, Y => 
                           n420_port);
   U564 : NAND2X1 port map( A => n418_port, B => n399, Y => n424_port);
   U565 : NAND2X1 port map( A => N1495, B => n399, Y => n418_port);
   U566 : NAND3X1 port map( A => IN0ByteCount_4_port, B => n324, C => 
                           IN0ByteCount_5_port, Y => n399);
   U567 : NAND2X1 port map( A => n372, B => n370, Y => n324);
   U568 : OAI21X1 port map( A => n425_port, B => n426_port, C => n427_port, Y 
                           => n964);
   U569 : NAND2X1 port map( A => n426_port, B => n428_port, Y => n427_port);
   U570 : INVX1 port map( A => IN1ByteCount_0_port, Y => n426_port);
   U571 : OAI21X1 port map( A => n425_port, B => n429, C => n430, Y => n963);
   U572 : NAND2X1 port map( A => N897, B => n428_port, Y => n430);
   U573 : INVX1 port map( A => IN1ByteCount_1_port, Y => n429);
   U574 : OAI21X1 port map( A => n425_port, B => n431, C => n432_port, Y => 
                           n962);
   U575 : NAND2X1 port map( A => N898, B => n428_port, Y => n432_port);
   U576 : OAI21X1 port map( A => n425_port, B => n433_port, C => n434_port, Y 
                           => n961);
   U577 : NAND2X1 port map( A => N899, B => n428_port, Y => n434_port);
   U578 : OAI21X1 port map( A => n425_port, B => n318, C => n435_port, Y => 
                           n960);
   U579 : NAND2X1 port map( A => N900, B => n428_port, Y => n435_port);
   U580 : OAI21X1 port map( A => n425_port, B => n319, C => n436_port, Y => 
                           n959);
   U581 : NAND2X1 port map( A => N901, B => n428_port, Y => n436_port);
   U582 : OAI21X1 port map( A => n323, B => n437_port, C => n89, Y => n428_port
                           );
   U583 : OAI21X1 port map( A => n90, B => n37, C => n438_port, Y => n958);
   U584 : AOI22X1 port map( A => RIRB1addr_0_port, B => n82, C => N971, D => 
                           n84, Y => n438_port);
   U585 : OAI21X1 port map( A => n89, B => n34, C => n440_port, Y => n957);
   U586 : AOI22X1 port map( A => RIRB1addr_1_port, B => n82, C => N972, D => 
                           n84, Y => n440_port);
   U587 : NAND2X1 port map( A => n441_port, B => n442_port, Y => n956);
   U588 : AOI21X1 port map( A => RIRB1addr_2_port, B => n443_port, C => n83, Y 
                           => n442_port);
   U589 : AOI22X1 port map( A => N973, B => n84, C => N911, D => n362, Y => 
                           n441_port);
   U590 : OAI21X1 port map( A => n91, B => n43, C => n445, Y => n955);
   U591 : AOI22X1 port map( A => RIRB1addr_3_port, B => n82, C => N974, D => 
                           n84, Y => n445);
   U592 : OAI21X1 port map( A => n89, B => n33, C => n446, Y => n954);
   U593 : AOI22X1 port map( A => RIRB1addr_4_port, B => n82, C => N975, D => 
                           n84, Y => n446);
   U594 : OAI21X1 port map( A => n90, B => n42, C => n447, Y => n953);
   U595 : AOI22X1 port map( A => RIRB1addr_5_port, B => n82, C => N976, D => 
                           n84, Y => n447);
   U596 : NAND2X1 port map( A => n448, B => n449, Y => n952);
   U597 : AOI21X1 port map( A => RIRB1addr_6_port, B => n443_port, C => n83, Y 
                           => n449);
   U598 : NAND2X1 port map( A => n425_port, B => n450, Y => n443_port);
   U599 : AOI22X1 port map( A => N977, B => n84, C => N915, D => n362, Y => 
                           n448);
   U600 : OAI21X1 port map( A => n89, B => n32, C => n451, Y => n951);
   U601 : AOI22X1 port map( A => RIRB1addr_7_port, B => n82, C => N978, D => 
                           n84, Y => n451);
   U602 : OAI21X1 port map( A => n91, B => n41, C => n452, Y => n950);
   U603 : AOI22X1 port map( A => RIRB1addr_8_port, B => n82, C => N979, D => 
                           n84, Y => n452);
   U604 : OAI21X1 port map( A => n91, B => n40, C => n453, Y => n949);
   U605 : AOI22X1 port map( A => RIRB1addr_9_port, B => n82, C => N980, D => 
                           n84, Y => n453);
   U606 : OAI21X1 port map( A => n90, B => n29, C => n454, Y => n948);
   U607 : AOI22X1 port map( A => RIRB1addr_10_port, B => n82, C => N981, D => 
                           n84, Y => n454);
   U608 : OAI21X1 port map( A => n77, B => n90, C => n455, Y => n947);
   U609 : AOI22X1 port map( A => RIRB1addr_11_port, B => n82, C => N982, D => 
                           n84, Y => n455);
   U610 : OAI21X1 port map( A => n323, B => n450, C => n425_port, Y => 
                           n439_port);
   U611 : INVX1 port map( A => n456, Y => n323);
   U612 : NAND2X1 port map( A => n457, B => n458, Y => n946);
   U613 : AOI21X1 port map( A => IN1addr_0_port, B => n459, C => n83, Y => n458
                           );
   U614 : AOI22X1 port map( A => N988, B => n85, C => N921, D => n362, Y => 
                           n457);
   U615 : NAND2X1 port map( A => n460, B => n461, Y => n945);
   U616 : AOI21X1 port map( A => IN1addr_1_port, B => n459, C => n83, Y => n461
                           );
   U617 : AOI22X1 port map( A => N989, B => n85, C => N922, D => n362, Y => 
                           n460);
   U618 : NAND2X1 port map( A => n462, B => n463, Y => n944);
   U619 : AOI21X1 port map( A => IN1addr_2_port, B => n459, C => n83, Y => n463
                           );
   U620 : AOI22X1 port map( A => N990, B => n85, C => N923, D => n362, Y => 
                           n462);
   U621 : NAND2X1 port map( A => n464, B => n465, Y => n943);
   U622 : AOI21X1 port map( A => IN1addr_3_port, B => n459, C => n83, Y => n465
                           );
   U623 : AOI22X1 port map( A => N991, B => n85, C => N924, D => n362, Y => 
                           n464);
   U624 : NAND2X1 port map( A => n466, B => n467, Y => n942);
   U625 : AOI21X1 port map( A => IN1addr_4_port, B => n459, C => n83, Y => n467
                           );
   U626 : AOI22X1 port map( A => N992, B => n85, C => N925, D => n362, Y => 
                           n466);
   U627 : NAND2X1 port map( A => n468, B => n469, Y => n941);
   U628 : AOI21X1 port map( A => IN1addr_5_port, B => n459, C => n83, Y => n469
                           );
   U629 : AOI22X1 port map( A => N993, B => n85, C => N926, D => n362, Y => 
                           n468);
   U630 : OAI21X1 port map( A => n89, B => n36, C => n470, Y => n940);
   U631 : AOI22X1 port map( A => IN1addr_6_port, B => n471, C => N994, D => n85
                           , Y => n470);
   U632 : OAI21X1 port map( A => n91, B => n44, C => n472, Y => n939);
   U633 : AOI22X1 port map( A => IN1addr_7_port, B => n471, C => N995, D => n85
                           , Y => n472);
   U634 : NAND2X1 port map( A => n473, B => n474, Y => n938);
   U635 : AOI21X1 port map( A => IN1addr_8_port, B => n459, C => n83, Y => n474
                           );
   U636 : NOR2X1 port map( A => n450, B => n475, Y => n444);
   U637 : INVX1 port map( A => n476, Y => n475);
   U638 : AOI22X1 port map( A => N996, B => n85, C => N929, D => n362, Y => 
                           n473);
   U639 : OAI21X1 port map( A => n89, B => n35, C => n477, Y => n937);
   U640 : AOI22X1 port map( A => IN1addr_9_port, B => n471, C => N997, D => n85
                           , Y => n477);
   U641 : OAI21X1 port map( A => n90, B => n58, C => n478, Y => n936);
   U642 : AOI22X1 port map( A => IN1addr_10_port, B => n471, C => N998, D => 
                           n85, Y => n478);
   U643 : OAI21X1 port map( A => n65, B => n89, C => n479, Y => n935);
   U644 : AOI22X1 port map( A => IN1addr_11_port, B => n471, C => N999, D => 
                           n85, Y => n479);
   U645 : NAND2X1 port map( A => n321, B => N1497, Y => n450);
   U646 : OAI21X1 port map( A => n437_port, B => n480, C => n425_port, Y => 
                           n471);
   U647 : NAND3X1 port map( A => n63, B => n92, C => n481, Y => n357);
   U648 : NOR2X1 port map( A => n314, B => n342, Y => n481);
   U649 : NAND2X1 port map( A => n476, B => n456, Y => n480);
   U650 : NAND2X1 port map( A => N1497, B => n456, Y => n476);
   U651 : NAND3X1 port map( A => IN1ByteCount_4_port, B => n317, C => 
                           IN1ByteCount_5_port, Y => n456);
   U652 : NAND2X1 port map( A => n433_port, B => n431, Y => n317);
   U653 : INVX1 port map( A => n482, Y => n934);
   U654 : MUX2X1 port map( B => OUTDATA_15_port, A => DATA_in(7), S => n483, Y 
                           => n482);
   U655 : INVX1 port map( A => n484, Y => n933);
   U656 : MUX2X1 port map( B => OUTDATA_14_port, A => DATA_in(6), S => n483, Y 
                           => n484);
   U657 : INVX1 port map( A => n485, Y => n932);
   U658 : MUX2X1 port map( B => OUTDATA_13_port, A => DATA_in(5), S => n483, Y 
                           => n485);
   U659 : INVX1 port map( A => n486, Y => n931);
   U660 : MUX2X1 port map( B => OUTDATA_12_port, A => DATA_in(4), S => n483, Y 
                           => n486);
   U661 : INVX1 port map( A => n487, Y => n930);
   U662 : MUX2X1 port map( B => OUTDATA_11_port, A => DATA_in(3), S => n483, Y 
                           => n487);
   U663 : INVX1 port map( A => n488, Y => n929_port);
   U664 : MUX2X1 port map( B => OUTDATA_10_port, A => DATA_in(2), S => n483, Y 
                           => n488);
   U665 : INVX1 port map( A => n489, Y => n928);
   U666 : MUX2X1 port map( B => OUTDATA_9_port, A => DATA_in(1), S => n483, Y 
                           => n489);
   U667 : INVX1 port map( A => n490, Y => n927);
   U668 : MUX2X1 port map( B => OUTDATA_8_port, A => DATA_in(0), S => n483, Y 
                           => n490);
   U669 : NOR2X1 port map( A => n491, B => n492, Y => n483);
   U670 : INVX1 port map( A => n493, Y => n926_port);
   U671 : MUX2X1 port map( B => DATA_in(7), A => OUTDATA_7_port, S => n494, Y 
                           => n493);
   U672 : INVX1 port map( A => n495, Y => n925_port);
   U673 : MUX2X1 port map( B => DATA_in(6), A => OUTDATA_6_port, S => n494, Y 
                           => n495);
   U674 : INVX1 port map( A => n496, Y => n924_port);
   U675 : MUX2X1 port map( B => DATA_in(5), A => OUTDATA_5_port, S => n494, Y 
                           => n496);
   U676 : INVX1 port map( A => n497, Y => n923_port);
   U677 : MUX2X1 port map( B => DATA_in(4), A => OUTDATA_4_port, S => n494, Y 
                           => n497);
   U678 : INVX1 port map( A => n498, Y => n922_port);
   U679 : MUX2X1 port map( B => DATA_in(3), A => OUTDATA_3_port, S => n494, Y 
                           => n498);
   U680 : INVX1 port map( A => n499, Y => n921_port);
   U681 : MUX2X1 port map( B => DATA_in(2), A => OUTDATA_2_port, S => n494, Y 
                           => n499);
   U682 : INVX1 port map( A => n500, Y => n920);
   U683 : MUX2X1 port map( B => DATA_in(1), A => OUTDATA_1_port, S => n494, Y 
                           => n500);
   U684 : INVX1 port map( A => n501, Y => n919);
   U685 : MUX2X1 port map( B => DATA_in(0), A => OUTDATA_0_port, S => n494, Y 
                           => n501);
   U686 : NAND3X1 port map( A => n502, B => n503, C => n504, Y => n494);
   U687 : NAND3X1 port map( A => n505, B => n506, C => n507, Y => n918);
   U688 : AOI22X1 port map( A => I1DATA(7), B => n508, C => I1DATA(15), D => 
                           n509, Y => n507);
   U689 : NAND2X1 port map( A => I0DATA(15), B => n510, Y => n506);
   U690 : AOI22X1 port map( A => DATA_out_7_port, B => n511, C => I0DATA(7), D 
                           => n512, Y => n505);
   U691 : NAND3X1 port map( A => n513, B => n514, C => n515, Y => n917);
   U692 : AOI22X1 port map( A => I1DATA(6), B => n508, C => I1DATA(14), D => 
                           n509, Y => n515);
   U693 : NAND2X1 port map( A => I0DATA(14), B => n510, Y => n514);
   U694 : AOI22X1 port map( A => DATA_out_6_port, B => n511, C => I0DATA(6), D 
                           => n512, Y => n513);
   U695 : NAND3X1 port map( A => n516, B => n517, C => n518, Y => n916);
   U696 : AOI22X1 port map( A => I1DATA(5), B => n508, C => I1DATA(13), D => 
                           n509, Y => n518);
   U697 : NAND2X1 port map( A => I0DATA(13), B => n510, Y => n517);
   U698 : AOI22X1 port map( A => DATA_out_5_port, B => n511, C => I0DATA(5), D 
                           => n512, Y => n516);
   U699 : NAND3X1 port map( A => n519, B => n520, C => n521, Y => n915_port);
   U700 : AOI22X1 port map( A => I1DATA(4), B => n508, C => I1DATA(12), D => 
                           n509, Y => n521);
   U701 : NAND2X1 port map( A => I0DATA(12), B => n510, Y => n520);
   U702 : AOI22X1 port map( A => DATA_out_4_port, B => n511, C => I0DATA(4), D 
                           => n512, Y => n519);
   U703 : NAND3X1 port map( A => n522, B => n523, C => n524, Y => n914);
   U704 : AOI22X1 port map( A => I1DATA(3), B => n508, C => I1DATA(11), D => 
                           n509, Y => n524);
   U705 : NAND2X1 port map( A => I0DATA(11), B => n510, Y => n523);
   U706 : AOI22X1 port map( A => DATA_out_3_port, B => n511, C => I0DATA(3), D 
                           => n512, Y => n522);
   U707 : NAND3X1 port map( A => n525, B => n526, C => n527, Y => n913);
   U708 : AOI22X1 port map( A => I1DATA(2), B => n508, C => I1DATA(10), D => 
                           n509, Y => n527);
   U709 : NAND2X1 port map( A => I0DATA(10), B => n510, Y => n526);
   U710 : AOI22X1 port map( A => DATA_out_2_port, B => n511, C => I0DATA(2), D 
                           => n512, Y => n525);
   U711 : NAND3X1 port map( A => n528, B => n529, C => n530, Y => n912);
   U712 : AOI22X1 port map( A => I1DATA(1), B => n508, C => I1DATA(9), D => 
                           n509, Y => n530);
   U713 : NAND2X1 port map( A => I0DATA(9), B => n510, Y => n529);
   U714 : AOI22X1 port map( A => DATA_out_1_port, B => n511, C => I0DATA(1), D 
                           => n512, Y => n528);
   U715 : NAND3X1 port map( A => n531, B => n532, C => n533, Y => n911_port);
   U716 : AOI22X1 port map( A => I1DATA(0), B => n508, C => I1DATA(8), D => 
                           n509, Y => n533);
   U717 : NAND2X1 port map( A => I0DATA(8), B => n510, Y => n532);
   U718 : AOI22X1 port map( A => DATA_out_0_port, B => n511, C => I0DATA(0), D 
                           => n512, Y => n531);
   U719 : INVX1 port map( A => n534, Y => n512);
   U720 : NAND2X1 port map( A => n535, B => n536, Y => n511);
   U721 : NAND3X1 port map( A => n537, B => n538, C => n539, Y => n910);
   U722 : NOR2X1 port map( A => n540, B => n541, Y => n539);
   U723 : OAI22X1 port map( A => n542, B => n543, C => n544, D => n545, Y => 
                           n541);
   U724 : INVX1 port map( A => CORBaddr_0_port, Y => n545);
   U725 : INVX1 port map( A => OUT2addr_0_port, Y => n543);
   U726 : OAI22X1 port map( A => n546, B => n547, C => n548, D => n549, Y => 
                           n540);
   U727 : INVX1 port map( A => IN0addr_0_port, Y => n548);
   U728 : INVX1 port map( A => RIRBaddr_0_port, Y => n546);
   U729 : AOI22X1 port map( A => ADDR_0_port, B => n550, C => n86, D => 
                           RIRB1addr_0_port, Y => n538);
   U730 : AOI22X1 port map( A => OUTaddr_0_port, B => n6, C => n87, D => 
                           IN1addr_0_port, Y => n537);
   U731 : NAND3X1 port map( A => n551, B => n552, C => n553, Y => n909);
   U732 : NOR2X1 port map( A => n554, B => n555, Y => n553);
   U733 : OAI22X1 port map( A => n542, B => n556, C => n544, D => n557, Y => 
                           n555);
   U734 : INVX1 port map( A => CORBaddr_1_port, Y => n557);
   U735 : INVX1 port map( A => OUT2addr_1_port, Y => n556);
   U736 : OAI22X1 port map( A => n558, B => n547, C => n559, D => n549, Y => 
                           n554);
   U737 : INVX1 port map( A => IN0addr_1_port, Y => n559);
   U738 : INVX1 port map( A => RIRBaddr_1_port, Y => n558);
   U739 : AOI22X1 port map( A => ADDR_1_port, B => n550, C => n86, D => 
                           RIRB1addr_1_port, Y => n552);
   U740 : AOI22X1 port map( A => OUTaddr_1_port, B => n6, C => n87, D => 
                           IN1addr_1_port, Y => n551);
   U741 : NAND3X1 port map( A => n560, B => n561, C => n562, Y => n908);
   U742 : NOR2X1 port map( A => n563, B => n564, Y => n562);
   U743 : OAI22X1 port map( A => n542, B => n565, C => n544, D => n566, Y => 
                           n564);
   U744 : INVX1 port map( A => CORBaddr_2_port, Y => n566);
   U745 : INVX1 port map( A => OUT2addr_2_port, Y => n565);
   U746 : OAI22X1 port map( A => n567, B => n547, C => n568, D => n549, Y => 
                           n563);
   U747 : INVX1 port map( A => IN0addr_2_port, Y => n568);
   U748 : INVX1 port map( A => RIRBaddr_2_port, Y => n567);
   U749 : AOI22X1 port map( A => ADDR_2_port, B => n550, C => n86, D => 
                           RIRB1addr_2_port, Y => n561);
   U750 : AOI22X1 port map( A => OUTaddr_2_port, B => n6, C => n87, D => 
                           IN1addr_2_port, Y => n560);
   U751 : NAND3X1 port map( A => n569, B => n570, C => n571, Y => n907);
   U752 : NOR2X1 port map( A => n572, B => n573, Y => n571);
   U753 : OAI22X1 port map( A => n542, B => n574, C => n544, D => n575, Y => 
                           n573);
   U754 : INVX1 port map( A => CORBaddr_3_port, Y => n575);
   U755 : INVX1 port map( A => OUT2addr_3_port, Y => n574);
   U756 : OAI22X1 port map( A => n576, B => n547, C => n577, D => n549, Y => 
                           n572);
   U757 : INVX1 port map( A => IN0addr_3_port, Y => n577);
   U758 : INVX1 port map( A => RIRBaddr_3_port, Y => n576);
   U759 : AOI22X1 port map( A => ADDR_3_port, B => n550, C => n86, D => 
                           RIRB1addr_3_port, Y => n570);
   U760 : AOI22X1 port map( A => OUTaddr_3_port, B => n6, C => n87, D => 
                           IN1addr_3_port, Y => n569);
   U761 : NAND3X1 port map( A => n578, B => n579, C => n580, Y => n906);
   U762 : NOR2X1 port map( A => n581, B => n582, Y => n580);
   U763 : OAI22X1 port map( A => n542, B => n583, C => n544, D => n584, Y => 
                           n582);
   U764 : INVX1 port map( A => CORBaddr_4_port, Y => n584);
   U765 : INVX1 port map( A => OUT2addr_4_port, Y => n583);
   U766 : OAI22X1 port map( A => n585, B => n547, C => n586, D => n549, Y => 
                           n581);
   U767 : INVX1 port map( A => IN0addr_4_port, Y => n586);
   U768 : INVX1 port map( A => RIRBaddr_4_port, Y => n585);
   U769 : AOI22X1 port map( A => ADDR_4_port, B => n550, C => n86, D => 
                           RIRB1addr_4_port, Y => n579);
   U770 : AOI22X1 port map( A => OUTaddr_4_port, B => n6, C => n87, D => 
                           IN1addr_4_port, Y => n578);
   U771 : NAND3X1 port map( A => n587, B => n588, C => n589, Y => n905);
   U772 : NOR2X1 port map( A => n590, B => n591, Y => n589);
   U773 : OAI22X1 port map( A => n542, B => n592, C => n544, D => n593, Y => 
                           n591);
   U774 : INVX1 port map( A => CORBaddr_5_port, Y => n593);
   U775 : INVX1 port map( A => OUT2addr_5_port, Y => n592);
   U776 : OAI22X1 port map( A => n594, B => n547, C => n595, D => n549, Y => 
                           n590);
   U777 : INVX1 port map( A => IN0addr_5_port, Y => n595);
   U778 : INVX1 port map( A => RIRBaddr_5_port, Y => n594);
   U779 : AOI22X1 port map( A => ADDR_5_port, B => n550, C => n86, D => 
                           RIRB1addr_5_port, Y => n588);
   U780 : AOI22X1 port map( A => OUTaddr_5_port, B => n6, C => n87, D => 
                           IN1addr_5_port, Y => n587);
   U781 : NAND3X1 port map( A => n596, B => n597, C => n598, Y => n904);
   U782 : NOR2X1 port map( A => n599, B => n600, Y => n598);
   U783 : OAI22X1 port map( A => n542, B => n601, C => n544, D => n602, Y => 
                           n600);
   U784 : INVX1 port map( A => CORBaddr_6_port, Y => n602);
   U785 : INVX1 port map( A => OUT2addr_6_port, Y => n601);
   U786 : OAI22X1 port map( A => n603, B => n547, C => n604, D => n549, Y => 
                           n599);
   U787 : INVX1 port map( A => IN0addr_6_port, Y => n604);
   U788 : INVX1 port map( A => RIRBaddr_6_port, Y => n603);
   U789 : AOI22X1 port map( A => ADDR_6_port, B => n550, C => n86, D => 
                           RIRB1addr_6_port, Y => n597);
   U790 : AOI22X1 port map( A => OUTaddr_6_port, B => n6, C => n87, D => 
                           IN1addr_6_port, Y => n596);
   U791 : NAND3X1 port map( A => n605, B => n606, C => n607, Y => n903);
   U792 : NOR2X1 port map( A => n608, B => n609, Y => n607);
   U793 : OAI22X1 port map( A => n542, B => n610, C => n544, D => n611, Y => 
                           n609);
   U794 : INVX1 port map( A => CORBaddr_7_port, Y => n611);
   U795 : INVX1 port map( A => OUT2addr_7_port, Y => n610);
   U796 : OAI22X1 port map( A => n612, B => n547, C => n613, D => n549, Y => 
                           n608);
   U797 : INVX1 port map( A => IN0addr_7_port, Y => n613);
   U798 : INVX1 port map( A => RIRBaddr_7_port, Y => n612);
   U799 : AOI22X1 port map( A => ADDR_7_port, B => n550, C => n86, D => 
                           RIRB1addr_7_port, Y => n606);
   U800 : AOI22X1 port map( A => OUTaddr_7_port, B => n6, C => n87, D => 
                           IN1addr_7_port, Y => n605);
   U801 : NAND3X1 port map( A => n614, B => n615, C => n616, Y => n902);
   U802 : NOR2X1 port map( A => n617, B => n618, Y => n616);
   U803 : OAI22X1 port map( A => n542, B => n619, C => n544, D => n620, Y => 
                           n618);
   U804 : INVX1 port map( A => CORBaddr_8_port, Y => n620);
   U805 : INVX1 port map( A => OUT2addr_8_port, Y => n619);
   U806 : OAI22X1 port map( A => n621, B => n547, C => n622, D => n549, Y => 
                           n617);
   U807 : INVX1 port map( A => IN0addr_8_port, Y => n622);
   U808 : INVX1 port map( A => RIRBaddr_8_port, Y => n621);
   U809 : AOI22X1 port map( A => ADDR_8_port, B => n550, C => n86, D => 
                           RIRB1addr_8_port, Y => n615);
   U810 : AOI22X1 port map( A => OUTaddr_8_port, B => n6, C => n87, D => 
                           IN1addr_8_port, Y => n614);
   U811 : NAND3X1 port map( A => n623, B => n624, C => n625, Y => n901_port);
   U812 : NOR2X1 port map( A => n626, B => n627, Y => n625);
   U813 : OAI22X1 port map( A => n542, B => n628, C => n544, D => n629, Y => 
                           n627);
   U814 : INVX1 port map( A => CORBaddr_9_port, Y => n629);
   U815 : INVX1 port map( A => OUT2addr_9_port, Y => n628);
   U816 : OAI22X1 port map( A => n630_port, B => n547, C => n631, D => n549, Y 
                           => n626);
   U817 : INVX1 port map( A => IN0addr_9_port, Y => n631);
   U818 : INVX1 port map( A => RIRBaddr_9_port, Y => n630_port);
   U819 : AOI22X1 port map( A => ADDR_9_port, B => n550, C => n86, D => 
                           RIRB1addr_9_port, Y => n624);
   U820 : AOI22X1 port map( A => OUTaddr_9_port, B => n6, C => n87, D => 
                           IN1addr_9_port, Y => n623);
   U821 : NAND3X1 port map( A => n632, B => n633, C => n634, Y => n900_port);
   U822 : NOR2X1 port map( A => n635, B => n636, Y => n634);
   U823 : OAI22X1 port map( A => n542, B => n637, C => n544, D => n638, Y => 
                           n636);
   U824 : INVX1 port map( A => CORBaddr_10_port, Y => n638);
   U825 : INVX1 port map( A => OUT2addr_10_port, Y => n637);
   U826 : OAI22X1 port map( A => n639, B => n547, C => n640, D => n549, Y => 
                           n635);
   U827 : INVX1 port map( A => IN0addr_10_port, Y => n640);
   U828 : INVX1 port map( A => RIRBaddr_10_port, Y => n639);
   U829 : AOI22X1 port map( A => ADDR_10_port, B => n550, C => n86, D => 
                           RIRB1addr_10_port, Y => n633);
   U830 : AOI22X1 port map( A => OUTaddr_10_port, B => n6, C => n87, D => 
                           IN1addr_10_port, Y => n632);
   U831 : NAND3X1 port map( A => n641, B => n642, C => n643, Y => n899_port);
   U832 : NOR2X1 port map( A => n644, B => n645, Y => n643);
   U833 : OAI22X1 port map( A => n542, B => n646, C => n544, D => n647, Y => 
                           n645);
   U834 : INVX1 port map( A => CORBaddr_11_port, Y => n647);
   U835 : NAND2X1 port map( A => add_377_aco_B_0_port, B => n648, Y => n544);
   U836 : INVX1 port map( A => OUT2addr_11_port, Y => n646);
   U837 : NAND2X1 port map( A => n648, B => N1499, Y => n542);
   U838 : OAI22X1 port map( A => n650, B => n547, C => n651, D => n549, Y => 
                           n644);
   U839 : NAND2X1 port map( A => N1495, B => n652, Y => n549);
   U840 : INVX1 port map( A => IN0addr_11_port, Y => n651);
   U841 : NAND2X1 port map( A => n652, B => N630, Y => n547);
   U842 : INVX1 port map( A => RIRBaddr_11_port, Y => n650);
   U843 : AOI22X1 port map( A => ADDR_11_port, B => n550, C => n86, D => 
                           RIRB1addr_11_port, Y => n642);
   U844 : NOR2X1 port map( A => n654, B => n492, Y => n535);
   U845 : AOI22X1 port map( A => OUTaddr_11_port, B => n6, C => n87, D => 
                           IN1addr_11_port, Y => n641);
   U846 : INVX1 port map( A => n648, Y => n536);
   U847 : NAND3X1 port map( A => n656, B => n657, C => n658, Y => n1050);
   U848 : NOR2X1 port map( A => n659, B => n660_port, Y => n658);
   U849 : OAI21X1 port map( A => n661_port, B => n662_port, C => n91, Y => 
                           n660_port);
   U850 : NAND2X1 port map( A => n663_port, B => n664_port, Y => n659);
   U851 : NOR2X1 port map( A => n492, B => n665, Y => n657);
   U852 : INVX1 port map( A => n653, Y => n665);
   U853 : NOR2X1 port map( A => n666, B => n667, Y => n656);
   U854 : OR2X1 port map( A => n668, B => n669, Y => n1049);
   U855 : OAI21X1 port map( A => n670, B => n671, C => n672_port, Y => n669);
   U856 : INVX1 port map( A => n666, Y => n672_port);
   U857 : OAI21X1 port map( A => n673_port, B => n674_port, C => n675_port, Y 
                           => n668);
   U858 : NOR2X1 port map( A => n299, B => n510, Y => n675_port);
   U859 : NAND2X1 port map( A => n677_port, B => n678, Y => n674_port);
   U860 : NAND3X1 port map( A => n679, B => n680, C => n681, Y => n1048);
   U861 : NOR2X1 port map( A => n682, B => n683, Y => n681);
   U862 : OAI21X1 port map( A => n670, B => n684_port, C => n685_port, Y => 
                           n683);
   U863 : OAI21X1 port map( A => n662_port, B => n686_port, C => n92, Y => n682
                           );
   U864 : NOR2X1 port map( A => n687_port, B => n688_port, Y => n680);
   U865 : NOR2X1 port map( A => n299, B => n508, Y => n679);
   U866 : OR2X1 port map( A => n667, B => n689_port, Y => n1047);
   U867 : OAI21X1 port map( A => n333_port, B => n690_port, C => n119, Y => 
                           n689_port);
   U868 : INVX1 port map( A => n691_port, Y => n119);
   U869 : OAI21X1 port map( A => n678, B => n333_port, C => n339, Y => 
                           n691_port);
   U870 : INVX1 port map( A => nextRE_i, Y => n339);
   U871 : INVX1 port map( A => n692, Y => n690_port);
   U872 : OAI21X1 port map( A => n337_port, B => n340, C => n670, Y => n667);
   U873 : INVX1 port map( A => n693, Y => n670);
   U874 : NAND2X1 port map( A => n692, B => n694, Y => n340);
   U875 : INVX1 port map( A => n695, Y => n337_port);
   U876 : NAND3X1 port map( A => n437_port, B => n376, C => n502, Y => n695);
   U877 : NAND3X1 port map( A => n696, B => n697, C => n698, Y => n1046);
   U878 : AOI21X1 port map( A => mainState_2_port, B => n693, C => n699, Y => 
                           n698);
   U879 : OAI21X1 port map( A => n700, B => n701, C => n534, Y => n699);
   U880 : OR2X1 port map( A => n662_port, B => n702, Y => n701);
   U881 : NAND3X1 port map( A => n673_port, B => n678, C => n677_port, Y => 
                           n662_port);
   U882 : INVX1 port map( A => n333_port, Y => n677_port);
   U883 : NAND2X1 port map( A => n363, B => n686_port, Y => n700);
   U884 : INVX1 port map( A => n703, Y => n363);
   U885 : OAI21X1 port map( A => n329, B => n335_port, C => n349, Y => n693);
   U886 : NAND2X1 port map( A => n692, B => n678, Y => n335_port);
   U887 : OR2X1 port map( A => n694, B => OUThold, Y => n678);
   U888 : NAND2X1 port map( A => OUTREQ, B => n704, Y => n694);
   U889 : NOR2X1 port map( A => n705, B => n661_port, Y => n692);
   U890 : OAI21X1 port map( A => n703, B => n702, C => n686_port, Y => 
                           n661_port);
   U891 : NAND2X1 port map( A => I0DRB, B => n354, Y => n686_port);
   U892 : INVX1 port map( A => I1DRW, Y => n702);
   U893 : OAI21X1 port map( A => n706, B => n703, C => n673_port, Y => n705);
   U894 : NAND2X1 port map( A => I0DRW, B => n354, Y => n673_port);
   U895 : NAND3X1 port map( A => n356, B => n707, C => n361, Y => n703);
   U896 : INVX1 port map( A => I1wait_0_port, Y => n361);
   U897 : INVX1 port map( A => I1wait_1_port, Y => n356);
   U898 : INVX1 port map( A => I1DRB, Y => n706);
   U899 : NOR2X1 port map( A => n293, B => n687_port, Y => n697);
   U900 : INVX1 port map( A => n298, Y => n293);
   U901 : NOR2X1 port map( A => n98, B => n509, Y => n696);
   U902 : OAI21X1 port map( A => n88, B => n708, C => n709, Y => n1045);
   U903 : NAND2X1 port map( A => N286, B => n710, Y => n709);
   U904 : INVX1 port map( A => outByteCount_0_port, Y => n708);
   U905 : OAI21X1 port map( A => n88, B => n711, C => n712, Y => n1044);
   U906 : NAND2X1 port map( A => N287, B => n710, Y => n712);
   U907 : INVX1 port map( A => outByteCount_1_port, Y => n711);
   U908 : OAI21X1 port map( A => n88, B => n713, C => n714, Y => n1043);
   U909 : NAND2X1 port map( A => N288, B => n710, Y => n714);
   U910 : INVX1 port map( A => outByteCount_2_port, Y => n713);
   U911 : OAI21X1 port map( A => n88, B => n715, C => n716, Y => n1042);
   U912 : NAND2X1 port map( A => N289, B => n710, Y => n716);
   U913 : OAI21X1 port map( A => n88, B => n717, C => n718, Y => n1041);
   U914 : NAND2X1 port map( A => N290, B => n710, Y => n718);
   U915 : OAI21X1 port map( A => n88, B => n75, C => n719, Y => n1040);
   U916 : NAND2X1 port map( A => N291, B => n710, Y => n719);
   U917 : OAI21X1 port map( A => n88, B => n720, C => n721, Y => n1039);
   U918 : NAND2X1 port map( A => N292, B => n710, Y => n721);
   U919 : OAI21X1 port map( A => n300, B => n288_port, C => n94, Y => n710);
   U920 : OAI21X1 port map( A => n94, B => n57, C => n723, Y => n1038);
   U921 : AOI22X1 port map( A => N432, B => n7, C => CORBaddr_0_port, D => n724
                           , Y => n723);
   U922 : OAI21X1 port map( A => n94, B => n56, C => n725, Y => n1037);
   U923 : AOI22X1 port map( A => N433, B => n7, C => CORBaddr_1_port, D => n724
                           , Y => n725);
   U924 : OAI21X1 port map( A => n94, B => n55, C => n726, Y => n1036);
   U925 : AOI22X1 port map( A => N434, B => n7, C => CORBaddr_2_port, D => n724
                           , Y => n726);
   U926 : OAI21X1 port map( A => n94, B => n54, C => n727, Y => n1035);
   U927 : AOI22X1 port map( A => N435, B => n7, C => CORBaddr_3_port, D => n724
                           , Y => n727);
   U928 : OAI21X1 port map( A => n94, B => n53, C => n728, Y => n1034);
   U929 : AOI22X1 port map( A => N436, B => n7, C => CORBaddr_4_port, D => n724
                           , Y => n728);
   U930 : OAI21X1 port map( A => n94, B => n52, C => n729, Y => n1033);
   U931 : AOI22X1 port map( A => N437, B => n7, C => CORBaddr_5_port, D => n724
                           , Y => n729);
   U932 : OAI21X1 port map( A => n94, B => n51, C => n730, Y => n1032);
   U933 : AOI22X1 port map( A => N438, B => n7, C => CORBaddr_6_port, D => n724
                           , Y => n730);
   U934 : OAI21X1 port map( A => n94, B => n50, C => n731, Y => n1031);
   U935 : AOI22X1 port map( A => N439, B => n7, C => CORBaddr_7_port, D => n724
                           , Y => n731);
   U936 : OAI21X1 port map( A => n94, B => n49, C => n732, Y => n1030);
   U937 : AOI22X1 port map( A => N440, B => n7, C => CORBaddr_8_port, D => n724
                           , Y => n732);
   U938 : OAI21X1 port map( A => n94, B => n11, C => n733, Y => n1029);
   U939 : AOI22X1 port map( A => N441, B => n7, C => CORBaddr_9_port, D => n724
                           , Y => n733);
   U940 : OAI21X1 port map( A => n94, B => n48, C => n734_port, Y => n1028);
   U941 : AOI22X1 port map( A => N442, B => n7, C => CORBaddr_10_port, D => 
                           n724, Y => n734_port);
   U942 : OAI21X1 port map( A => n94, B => n12, C => n735_port, Y => n1027);
   U943 : AOI22X1 port map( A => N443, B => n7, C => CORBaddr_11_port, D => 
                           n724, Y => n735_port);
   U944 : OAI21X1 port map( A => n288_port, B => n736_port, C => n88, Y => n724
                           );
   U945 : NAND2X1 port map( A => n649, B => n287_port, Y => n736_port);
   U946 : NAND3X1 port map( A => n717, B => n720, C => n738_port, Y => n649);
   U947 : NAND2X1 port map( A => n739_port, B => n740_port, Y => n1026);
   U948 : AOI21X1 port map( A => OUTaddr_0_port, B => n741_port, C => n10, Y =>
                           n740_port);
   U949 : AOI22X1 port map( A => N400, B => n5, C => N306, D => n98, Y => 
                           n739_port);
   U950 : NAND2X1 port map( A => n742_port, B => n743_port, Y => n1025);
   U951 : AOI21X1 port map( A => OUTaddr_1_port, B => n741_port, C => n10, Y =>
                           n743_port);
   U952 : AOI22X1 port map( A => N401, B => n5, C => N307, D => n97, Y => 
                           n742_port);
   U953 : NAND2X1 port map( A => n744_port, B => n745_port, Y => n1024);
   U954 : AOI21X1 port map( A => OUTaddr_2_port, B => n741_port, C => n10, Y =>
                           n745_port);
   U955 : AOI22X1 port map( A => N402, B => n5, C => N308, D => n97, Y => 
                           n744_port);
   U956 : NAND2X1 port map( A => n746, B => n747, Y => n1023);
   U957 : AOI21X1 port map( A => OUTaddr_3_port, B => n741_port, C => n10, Y =>
                           n747);
   U958 : AOI22X1 port map( A => N403, B => n5, C => N309, D => n97, Y => n746)
                           ;
   U959 : NAND2X1 port map( A => n748, B => n749, Y => n1022);
   U960 : AOI21X1 port map( A => OUTaddr_4_port, B => n741_port, C => n10, Y =>
                           n749);
   U961 : AOI22X1 port map( A => N404, B => n5, C => N310, D => n97, Y => n748)
                           ;
   U962 : NAND2X1 port map( A => n750, B => n751_port, Y => n1021);
   U963 : AOI21X1 port map( A => OUTaddr_5_port, B => n741_port, C => n10, Y =>
                           n751_port);
   U964 : AOI22X1 port map( A => N405, B => n5, C => N311, D => n97, Y => n750)
                           ;
   U965 : NAND2X1 port map( A => n752_port, B => n753_port, Y => n1020);
   U966 : AOI21X1 port map( A => OUTaddr_6_port, B => n741_port, C => n10, Y =>
                           n753_port);
   U967 : AOI22X1 port map( A => N406, B => n5, C => N312, D => n97, Y => 
                           n752_port);
   U968 : OAI21X1 port map( A => n94, B => n47, C => n754_port, Y => n1019);
   U969 : AOI22X1 port map( A => N407, B => n5, C => n755_port, D => 
                           OUTaddr_7_port, Y => n754_port);
   U970 : OAI21X1 port map( A => n94, B => n30, C => n756_port, Y => n1018);
   U971 : AOI22X1 port map( A => N408, B => n5, C => n755_port, D => 
                           OUTaddr_8_port, Y => n756_port);
   U972 : OAI21X1 port map( A => n94, B => n20, C => n757_port, Y => n1017);
   U973 : AOI22X1 port map( A => N409, B => n5, C => n755_port, D => 
                           OUTaddr_9_port, Y => n757_port);
   U974 : OAI21X1 port map( A => n94, B => n19, C => n758_port, Y => n1016);
   U975 : AOI22X1 port map( A => N410, B => n5, C => n755_port, D => 
                           OUTaddr_10_port, Y => n758_port);
   U976 : OAI21X1 port map( A => n94, B => n73, C => n759_port, Y => n1015);
   U977 : AOI22X1 port map( A => N411, B => n5, C => n755_port, D => 
                           OUTaddr_11_port, Y => n759_port);
   U978 : AOI21X1 port map( A => n88, B => n300, C => n760_port, Y => n755_port
                           );
   U979 : NAND2X1 port map( A => n737_port, B => n88, Y => n741_port);
   U980 : NAND2X1 port map( A => n761_port, B => n762_port, Y => n1014);
   U981 : AOI21X1 port map( A => OUT2addr_0_port, B => n763, C => n10, Y => 
                           n762_port);
   U982 : AOI22X1 port map( A => N417, B => n8, C => N330, D => n97, Y => 
                           n761_port);
   U983 : NAND2X1 port map( A => n764, B => n765, Y => n1013);
   U984 : AOI21X1 port map( A => OUT2addr_1_port, B => n763, C => n10, Y => 
                           n765);
   U985 : AOI22X1 port map( A => N418, B => n8, C => N331, D => n96, Y => n764)
                           ;
   U986 : NAND2X1 port map( A => n766, B => n767, Y => n1012);
   U987 : AOI21X1 port map( A => OUT2addr_2_port, B => n763, C => n10, Y => 
                           n767);
   U988 : AOI22X1 port map( A => N419, B => n8, C => N332, D => n96, Y => n766)
                           ;
   U989 : NAND2X1 port map( A => n768, B => n769, Y => n1011);
   U990 : AOI21X1 port map( A => OUT2addr_3_port, B => n763, C => n10, Y => 
                           n769);
   U991 : AOI22X1 port map( A => N420, B => n8, C => N333, D => n96, Y => n768)
                           ;
   U992 : NAND2X1 port map( A => n770, B => n771, Y => n1010);
   U993 : AOI21X1 port map( A => OUT2addr_4_port, B => n763, C => n10, Y => 
                           n771);
   U994 : AOI22X1 port map( A => N421, B => n8, C => N334, D => n95, Y => n770)
                           ;
   U995 : NAND2X1 port map( A => n772, B => n773, Y => n1009);
   U996 : AOI21X1 port map( A => OUT2addr_5_port, B => n763, C => n10, Y => 
                           n773);
   U997 : AOI22X1 port map( A => N422, B => n8, C => N335, D => n95, Y => n772)
                           ;
   U998 : OAI21X1 port map( A => n94, B => n23, C => n774, Y => n1008);
   U999 : AOI22X1 port map( A => N423, B => n8, C => OUT2addr_6_port, D => n775
                           , Y => n774);
   U1000 : NAND2X1 port map( A => n776, B => n777, Y => n1007);
   U1001 : AOI21X1 port map( A => OUT2addr_7_port, B => n763, C => n10, Y => 
                           n777);
   U1002 : OAI21X1 port map( A => n778, B => n288_port, C => n88, Y => n763);
   U1003 : INVX1 port map( A => n779, Y => n778);
   U1004 : AOI22X1 port map( A => N424, B => n8, C => N337, D => n95, Y => n776
                           );
   U1005 : OAI21X1 port map( A => n94, B => n22, C => n780, Y => n1006);
   U1006 : AOI22X1 port map( A => N425, B => n8, C => OUT2addr_8_port, D => 
                           n775, Y => n780);
   U1007 : OAI21X1 port map( A => n94, B => n21, C => n781, Y => n1005);
   U1008 : AOI22X1 port map( A => N426, B => n8, C => OUT2addr_9_port, D => 
                           n775, Y => n781);
   U1009 : OAI21X1 port map( A => n94, B => n24, C => n782, Y => n1004);
   U1010 : AOI22X1 port map( A => N427, B => n8, C => OUT2addr_10_port, D => 
                           n775, Y => n782);
   U1011 : OAI21X1 port map( A => n94, B => n3, C => n783, Y => n1003);
   U1012 : AOI22X1 port map( A => N428, B => n8, C => OUT2addr_11_port, D => 
                           n775, Y => n783);
   U1013 : OAI21X1 port map( A => n288_port, B => n784, C => n88, Y => n775);
   U1014 : INVX1 port map( A => n663_port, Y => n688_port);
   U1015 : NAND3X1 port map( A => n347, B => n298, C => n785, Y => n491);
   U1016 : INVX1 port map( A => n654, Y => n785);
   U1017 : NAND3X1 port map( A => n786, B => n502, C => n787, Y => n654);
   U1018 : NOR2X1 port map( A => n788, B => n666, Y => n787);
   U1019 : NAND2X1 port map( A => n120, B => n789, Y => n666);
   U1020 : NOR2X1 port map( A => WE_port, B => n687_port, Y => n786);
   U1021 : INVX1 port map( A => n664_port, Y => n687_port);
   U1022 : INVX1 port map( A => n303, Y => n347);
   U1023 : NAND2X1 port map( A => n779, B => n287_port, Y => n784);
   U1024 : NAND2X1 port map( A => n299, B => n655, Y => n737_port);
   U1025 : INVX1 port map( A => add_371_aco_B_0_port, Y => n655);
   U1026 : AOI21X1 port map( A => n717, B => n738_port, C => N1499, Y => 
                           add_371_aco_B_0_port);
   U1027 : NAND2X1 port map( A => N1499, B => n287_port, Y => n779);
   U1028 : INVX1 port map( A => n300, Y => n287_port);
   U1029 : NOR2X1 port map( A => n720, B => n791, Y => n300);
   U1030 : OAI21X1 port map( A => outByteCount_5_port, B => outByteCount_4_port
                           , C => n790, Y => n791);
   U1031 : NAND3X1 port map( A => n715, B => n75, C => n792, Y => n790);
   U1032 : XOR2X1 port map( A => n793, B => n348, Y => n1002);
   U1033 : OAI21X1 port map( A => n794, B => n795, C => n796, Y => n1001);
   U1034 : OAI21X1 port map( A => outwait_1_port, B => n348, C => 
                           outwait_2_port, Y => n796);
   U1035 : NAND2X1 port map( A => n797, B => n798, Y => n348);
   U1036 : OAI21X1 port map( A => WE_port, B => n794, C => n704, Y => n798);
   U1037 : NAND2X1 port map( A => n704, B => n503, Y => n795);
   U1038 : INVX1 port map( A => WE_port, Y => n503);
   U1039 : INVX1 port map( A => n799, Y => n704);
   U1040 : NAND3X1 port map( A => n793, B => n800, C => n797, Y => n799);
   U1041 : INVX1 port map( A => outwait_0_port, Y => n797);
   U1042 : NOR2X1 port map( A => n801, B => I0wait_0_port, Y => n1000);
   U1043 : INVX1 port map( A => n802, Y => n801);
   U1044 : OAI21X1 port map( A => n380, B => n350, C => n354, Y => n802);
   U1045 : NOR3X1 port map( A => I0wait_1_port, B => N1113, C => I0wait_0_port,
                           Y => n354);
   U1046 : NAND3X1 port map( A => n63, B => n91, C => n803, Y => n350);
   U1047 : NOR2X1 port map( A => n321, B => n342, Y => n803);
   U1048 : INVX1 port map( A => n502, Y => n342);
   U1049 : NAND3X1 port map( A => n93, B => n804, C => mainState_1_port, Y => 
                           n120);
   U1050 : NOR3X1 port map( A => n303, B => nextRE_i, C => n788, Y => n504);
   U1051 : NAND3X1 port map( A => n329, B => n333_port, C => n349, Y => n788);
   U1052 : NAND3X1 port map( A => n805, B => mainState_1_port, C => 
                           mainState_2_port, Y => n349);
   U1053 : NAND3X1 port map( A => n806, B => n684_port, C => n807, Y => 
                           n333_port);
   U1054 : NAND3X1 port map( A => n804, B => n671, C => n93, Y => n329);
   U1055 : NAND3X1 port map( A => n664_port, B => n789, C => n808, Y => 
                           nextRE_i);
   U1056 : NOR2X1 port map( A => n492, B => n648, Y => n808);
   U1057 : NAND2X1 port map( A => n663_port, B => n298, Y => n648);
   U1058 : NAND3X1 port map( A => n806, B => n93, C => n809, Y => n298);
   U1059 : NOR2X1 port map( A => mainState_4_port, B => mainState_3_port, Y => 
                           n809);
   U1060 : NAND2X1 port map( A => n810, B => n805, Y => n663_port);
   U1061 : NAND3X1 port map( A => n93, B => n811, C => n812, Y => n722);
   U1062 : NAND2X1 port map( A => n806, B => n805, Y => n288_port);
   U1063 : NAND2X1 port map( A => n805, B => n813, Y => n789);
   U1064 : INVX1 port map( A => n814, Y => n805);
   U1065 : NAND3X1 port map( A => n93, B => mainState_4_port, C => 
                           mainState_3_port, Y => n814);
   U1066 : NAND3X1 port map( A => n93, B => mainState_4_port, C => n812, Y => 
                           n664_port);
   U1067 : NAND2X1 port map( A => n653, B => n685_port, Y => n303);
   U1068 : INVX1 port map( A => n652, Y => n685_port);
   U1069 : NAND2X1 port map( A => n676_port, B => n534, Y => n652);
   U1070 : NAND2X1 port map( A => n815, B => n806, Y => n534);
   U1071 : NAND3X1 port map( A => n813, B => n684_port, C => n807, Y => 
                           n676_port);
   U1072 : NOR2X1 port map( A => n509, B => n508, Y => n653);
   U1073 : NAND3X1 port map( A => n817, B => n671, C => n804, Y => n816);
   U1074 : NAND3X1 port map( A => n92, B => n90, C => n818, Y => WE_port);
   U1075 : NOR2X1 port map( A => n314, B => n321, Y => n818);
   U1076 : INVX1 port map( A => n437_port, Y => n321);
   U1077 : NAND3X1 port map( A => mainState_4_port, B => n817, C => n812, Y => 
                           n346);
   U1078 : NOR2X1 port map( A => n671, B => mainState_2_port, Y => n813);
   U1079 : INVX1 port map( A => mainState_1_port, Y => n671);
   U1080 : NOR2X1 port map( A => n819, B => miniOUTstate_1_port, Y => 
                           REQ_Tx_DATA_port);
   U1081 : OAI21X1 port map( A => n793, B => n800, C => n502, Y => OUTSTRB);
   U1082 : NAND3X1 port map( A => n804, B => n817, C => mainState_1_port, Y => 
                           n502);
   U1083 : INVX1 port map( A => n93, Y => n817);
   U1084 : INVX1 port map( A => n820, Y => n804);
   U1085 : NAND3X1 port map( A => n821, B => n684_port, C => mainState_4_port, 
                           Y => n820);
   U1086 : INVX1 port map( A => outwait_2_port, Y => n800);
   U1087 : INVX1 port map( A => outwait_1_port, Y => n793);
   U1088 : NAND2X1 port map( A => n822, B => n720, Y => N1499);
   U1089 : INVX1 port map( A => outByteCount_6_port, Y => n720);
   U1090 : OAI21X1 port map( A => n823, B => n824, C => outByteCount_5_port, Y 
                           => n822);
   U1091 : INVX1 port map( A => n792, Y => n823);
   U1092 : OAI21X1 port map( A => outByteCount_1_port, B => outByteCount_0_port
                           , C => outByteCount_2_port, Y => n792);
   U1093 : NAND3X1 port map( A => n318, B => n319, C => n825, Y => N1497);
   U1094 : OAI21X1 port map( A => n431, B => n320, C => n433_port, Y => n826);
   U1095 : INVX1 port map( A => IN1ByteCount_3_port, Y => n433_port);
   U1096 : NOR2X1 port map( A => IN1ByteCount_1_port, B => IN1ByteCount_0_port,
                           Y => n320);
   U1097 : INVX1 port map( A => IN1ByteCount_2_port, Y => n431);
   U1098 : INVX1 port map( A => IN1ByteCount_5_port, Y => n319);
   U1099 : INVX1 port map( A => IN1ByteCount_4_port, Y => n318);
   U1100 : NAND3X1 port map( A => n325, B => n326, C => n827, Y => N1495);
   U1101 : OAI21X1 port map( A => n370, B => n327, C => n372, Y => n828);
   U1102 : INVX1 port map( A => IN0ByteCount_3_port, Y => n372);
   U1103 : NOR2X1 port map( A => IN0ByteCount_1_port, B => IN0ByteCount_0_port,
                           Y => n327);
   U1104 : INVX1 port map( A => IN0ByteCount_2_port, Y => n370);
   U1105 : INVX1 port map( A => IN0ByteCount_5_port, Y => n326);
   U1106 : INVX1 port map( A => IN0ByteCount_4_port, Y => n325);
   U1107 : NAND2X1 port map( A => n707, B => n437_port, Y => I1STRB);
   U1108 : NAND3X1 port map( A => n806, B => mainState_3_port, C => n829, Y => 
                           n437_port);
   U1109 : NOR2X1 port map( A => n93, B => n811, Y => n829);
   U1110 : INVX1 port map( A => mainState_4_port, Y => n811);
   U1111 : NOR2X1 port map( A => mainState_2_port, B => mainState_1_port, Y => 
                           n806);
   U1112 : INVX1 port map( A => N1124, Y => n707);
   U1113 : OR2X1 port map( A => N1113, B => n314, Y => I0STRB);
   U1114 : NAND2X1 port map( A => n815, B => n810, Y => n376);
   U1115 : NOR2X1 port map( A => n821, B => mainState_1_port, Y => n810);
   U1116 : NOR2X1 port map( A => mainState_4_port, B => n93, Y => n807);
   U1117 : MUX2X1 port map( B => n830, A => miniINstate_0_port, S => 
                           miniINstate_1_port, Y => ERR);
   U1118 : NAND2X1 port map( A => miniOUTstate_1_port, B => n819, Y => n830);
   U1119 : INVX1 port map( A => miniOUTstate_0_port, Y => n819);

end SYN_mcu_arch;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity IN_BLOCK_0 is

   port( BCLK, EN, RST, SDI, STRB, SYNC : in std_logic;  DATA : out 
         std_logic_vector (15 downto 0);  DataReadyB, DataReadyW : out 
         std_logic);

end IN_BLOCK_0;

architecture SYN_struct of IN_BLOCK_0 is

   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component SHIFT_REG_16_0
      port( CLK, RST_N, SHIFT_ENABLE, D_ORIG : in std_logic;  RCV_DATA : out 
            std_logic_vector (15 downto 0));
   end component;
   
   component SHIFT_REG_16_1
      port( CLK, RST_N, SHIFT_ENABLE, D_ORIG : in std_logic;  RCV_DATA : out 
            std_logic_vector (15 downto 0));
   end component;
   
   component InBlock_0
      port( RST, BCLK, EN, SYNC, STRB : in std_logic;  DataReadyB, DataReadyW, 
            Shift1En, Shift2En, ZeroPad : out std_logic);
   end component;
   
   component AOI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component NOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   signal ZeroPad, D_ORIG, SHIFT_ENABLE, RCV_DATA_15_port, RCV_DATA_14_port, 
      RCV_DATA_13_port, RCV_DATA_12_port, RCV_DATA_11_port, RCV_DATA_10_port, 
      RCV_DATA_9_port, RCV_DATA_8_port, RCV_DATA_7_port, RCV_DATA_6_port, 
      RCV_DATA_5_port, RCV_DATA_4_port, RCV_DATA_3_port, RCV_DATA_2_port, 
      RCV_DATA_1_port, RCV_DATA_0_port, RCV_DATA1_15_port, RCV_DATA1_14_port, 
      RCV_DATA1_13_port, RCV_DATA1_12_port, RCV_DATA1_11_port, 
      RCV_DATA1_10_port, RCV_DATA1_9_port, RCV_DATA1_8_port, RCV_DATA1_7_port, 
      RCV_DATA1_6_port, RCV_DATA1_5_port, RCV_DATA1_4_port, RCV_DATA1_3_port, 
      RCV_DATA1_2_port, RCV_DATA1_1_port, RCV_DATA1_0_port, SHIFT_ENABLE1, n19,
      n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34
      , n1, n2, n3, n36 : std_logic;

begin
   
   U19 : NOR2X1 port map( A => ZeroPad, B => n36, Y => D_ORIG);
   U20 : AOI22X1 port map( A => SHIFT_ENABLE, B => RCV_DATA1_9_port, C => 
                           RCV_DATA_9_port, D => n1, Y => n19);
   U21 : AOI22X1 port map( A => RCV_DATA1_8_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_8_port, D => n1, Y => n20);
   U22 : AOI22X1 port map( A => RCV_DATA1_7_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_7_port, D => n1, Y => n21);
   U23 : AOI22X1 port map( A => RCV_DATA1_6_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_6_port, D => n1, Y => n22);
   U24 : AOI22X1 port map( A => RCV_DATA1_5_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_5_port, D => n1, Y => n23);
   U25 : AOI22X1 port map( A => RCV_DATA1_4_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_4_port, D => n1, Y => n24);
   U26 : AOI22X1 port map( A => RCV_DATA1_3_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_3_port, D => n1, Y => n25);
   U27 : AOI22X1 port map( A => RCV_DATA1_2_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_2_port, D => n1, Y => n26);
   U28 : AOI22X1 port map( A => RCV_DATA1_1_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_1_port, D => n1, Y => n27);
   U29 : AOI22X1 port map( A => RCV_DATA1_15_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_15_port, D => n1, Y => n28);
   U30 : AOI22X1 port map( A => RCV_DATA1_14_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_14_port, D => n1, Y => n29);
   U31 : AOI22X1 port map( A => RCV_DATA1_13_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_13_port, D => n1, Y => n30);
   U32 : AOI22X1 port map( A => RCV_DATA1_12_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_12_port, D => n1, Y => n31);
   U33 : AOI22X1 port map( A => RCV_DATA1_11_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_11_port, D => n1, Y => n32);
   U34 : AOI22X1 port map( A => RCV_DATA1_10_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_10_port, D => n1, Y => n33);
   U35 : AOI22X1 port map( A => RCV_DATA1_0_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_0_port, D => n1, Y => n34);
   U_0 : InBlock_0 port map( RST => RST, BCLK => n2, EN => EN, SYNC => SYNC, 
                           STRB => STRB, DataReadyB => DataReadyB, DataReadyW 
                           => DataReadyW, Shift1En => SHIFT_ENABLE, Shift2En =>
                           SHIFT_ENABLE1, ZeroPad => ZeroPad);
   U_1 : SHIFT_REG_16_1 port map( CLK => n2, RST_N => RST, SHIFT_ENABLE => 
                           SHIFT_ENABLE, D_ORIG => D_ORIG, RCV_DATA(15) => 
                           RCV_DATA_15_port, RCV_DATA(14) => RCV_DATA_14_port, 
                           RCV_DATA(13) => RCV_DATA_13_port, RCV_DATA(12) => 
                           RCV_DATA_12_port, RCV_DATA(11) => RCV_DATA_11_port, 
                           RCV_DATA(10) => RCV_DATA_10_port, RCV_DATA(9) => 
                           RCV_DATA_9_port, RCV_DATA(8) => RCV_DATA_8_port, 
                           RCV_DATA(7) => RCV_DATA_7_port, RCV_DATA(6) => 
                           RCV_DATA_6_port, RCV_DATA(5) => RCV_DATA_5_port, 
                           RCV_DATA(4) => RCV_DATA_4_port, RCV_DATA(3) => 
                           RCV_DATA_3_port, RCV_DATA(2) => RCV_DATA_2_port, 
                           RCV_DATA(1) => RCV_DATA_1_port, RCV_DATA(0) => 
                           RCV_DATA_0_port);
   U_2 : SHIFT_REG_16_0 port map( CLK => n2, RST_N => RST, SHIFT_ENABLE => 
                           SHIFT_ENABLE1, D_ORIG => D_ORIG, RCV_DATA(15) => 
                           RCV_DATA1_15_port, RCV_DATA(14) => RCV_DATA1_14_port
                           , RCV_DATA(13) => RCV_DATA1_13_port, RCV_DATA(12) =>
                           RCV_DATA1_12_port, RCV_DATA(11) => RCV_DATA1_11_port
                           , RCV_DATA(10) => RCV_DATA1_10_port, RCV_DATA(9) => 
                           RCV_DATA1_9_port, RCV_DATA(8) => RCV_DATA1_8_port, 
                           RCV_DATA(7) => RCV_DATA1_7_port, RCV_DATA(6) => 
                           RCV_DATA1_6_port, RCV_DATA(5) => RCV_DATA1_5_port, 
                           RCV_DATA(4) => RCV_DATA1_4_port, RCV_DATA(3) => 
                           RCV_DATA1_3_port, RCV_DATA(2) => RCV_DATA1_2_port, 
                           RCV_DATA(1) => RCV_DATA1_1_port, RCV_DATA(0) => 
                           RCV_DATA1_0_port);
   U1 : INVX2 port map( A => n3, Y => n2);
   U2 : INVX2 port map( A => BCLK, Y => n3);
   U3 : INVX2 port map( A => SHIFT_ENABLE, Y => n1);
   U4 : INVX2 port map( A => n34, Y => DATA(0));
   U5 : INVX2 port map( A => n27, Y => DATA(1));
   U6 : INVX2 port map( A => n26, Y => DATA(2));
   U7 : INVX2 port map( A => n25, Y => DATA(3));
   U8 : INVX2 port map( A => n24, Y => DATA(4));
   U9 : INVX2 port map( A => n23, Y => DATA(5));
   U10 : INVX2 port map( A => n22, Y => DATA(6));
   U11 : INVX2 port map( A => n21, Y => DATA(7));
   U12 : INVX2 port map( A => n20, Y => DATA(8));
   U13 : INVX2 port map( A => n19, Y => DATA(9));
   U14 : INVX2 port map( A => n33, Y => DATA(10));
   U15 : INVX2 port map( A => n32, Y => DATA(11));
   U16 : INVX2 port map( A => n31, Y => DATA(12));
   U17 : INVX2 port map( A => n30, Y => DATA(13));
   U18 : INVX2 port map( A => n29, Y => DATA(14));
   U36 : INVX2 port map( A => n28, Y => DATA(15));
   U37 : INVX2 port map( A => SDI, Y => n36);

end SYN_struct;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity IN_BLOCK_1 is

   port( BCLK, EN, RST, SDI, STRB, SYNC : in std_logic;  DATA : out 
         std_logic_vector (15 downto 0);  DataReadyB, DataReadyW : out 
         std_logic);

end IN_BLOCK_1;

architecture SYN_struct of IN_BLOCK_1 is

   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component SHIFT_REG_16_2
      port( CLK, RST_N, SHIFT_ENABLE, D_ORIG : in std_logic;  RCV_DATA : out 
            std_logic_vector (15 downto 0));
   end component;
   
   component SHIFT_REG_16_3
      port( CLK, RST_N, SHIFT_ENABLE, D_ORIG : in std_logic;  RCV_DATA : out 
            std_logic_vector (15 downto 0));
   end component;
   
   component InBlock_1
      port( RST, BCLK, EN, SYNC, STRB : in std_logic;  DataReadyB, DataReadyW, 
            Shift1En, Shift2En, ZeroPad : out std_logic);
   end component;
   
   component AOI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component NOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   signal ZeroPad, D_ORIG, SHIFT_ENABLE, RCV_DATA_15_port, RCV_DATA_14_port, 
      RCV_DATA_13_port, RCV_DATA_12_port, RCV_DATA_11_port, RCV_DATA_10_port, 
      RCV_DATA_9_port, RCV_DATA_8_port, RCV_DATA_7_port, RCV_DATA_6_port, 
      RCV_DATA_5_port, RCV_DATA_4_port, RCV_DATA_3_port, RCV_DATA_2_port, 
      RCV_DATA_1_port, RCV_DATA_0_port, RCV_DATA1_15_port, RCV_DATA1_14_port, 
      RCV_DATA1_13_port, RCV_DATA1_12_port, RCV_DATA1_11_port, 
      RCV_DATA1_10_port, RCV_DATA1_9_port, RCV_DATA1_8_port, RCV_DATA1_7_port, 
      RCV_DATA1_6_port, RCV_DATA1_5_port, RCV_DATA1_4_port, RCV_DATA1_3_port, 
      RCV_DATA1_2_port, RCV_DATA1_1_port, RCV_DATA1_0_port, SHIFT_ENABLE1, n19,
      n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34
      , n1, n2, n3, n36 : std_logic;

begin
   
   U19 : NOR2X1 port map( A => ZeroPad, B => n36, Y => D_ORIG);
   U20 : AOI22X1 port map( A => SHIFT_ENABLE, B => RCV_DATA1_9_port, C => 
                           RCV_DATA_9_port, D => n1, Y => n19);
   U21 : AOI22X1 port map( A => RCV_DATA1_8_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_8_port, D => n1, Y => n20);
   U22 : AOI22X1 port map( A => RCV_DATA1_7_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_7_port, D => n1, Y => n21);
   U23 : AOI22X1 port map( A => RCV_DATA1_6_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_6_port, D => n1, Y => n22);
   U24 : AOI22X1 port map( A => RCV_DATA1_5_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_5_port, D => n1, Y => n23);
   U25 : AOI22X1 port map( A => RCV_DATA1_4_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_4_port, D => n1, Y => n24);
   U26 : AOI22X1 port map( A => RCV_DATA1_3_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_3_port, D => n1, Y => n25);
   U27 : AOI22X1 port map( A => RCV_DATA1_2_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_2_port, D => n1, Y => n26);
   U28 : AOI22X1 port map( A => RCV_DATA1_1_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_1_port, D => n1, Y => n27);
   U29 : AOI22X1 port map( A => RCV_DATA1_15_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_15_port, D => n1, Y => n28);
   U30 : AOI22X1 port map( A => RCV_DATA1_14_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_14_port, D => n1, Y => n29);
   U31 : AOI22X1 port map( A => RCV_DATA1_13_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_13_port, D => n1, Y => n30);
   U32 : AOI22X1 port map( A => RCV_DATA1_12_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_12_port, D => n1, Y => n31);
   U33 : AOI22X1 port map( A => RCV_DATA1_11_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_11_port, D => n1, Y => n32);
   U34 : AOI22X1 port map( A => RCV_DATA1_10_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_10_port, D => n1, Y => n33);
   U35 : AOI22X1 port map( A => RCV_DATA1_0_port, B => SHIFT_ENABLE, C => 
                           RCV_DATA_0_port, D => n1, Y => n34);
   U_0 : InBlock_1 port map( RST => RST, BCLK => n2, EN => EN, SYNC => SYNC, 
                           STRB => STRB, DataReadyB => DataReadyB, DataReadyW 
                           => DataReadyW, Shift1En => SHIFT_ENABLE, Shift2En =>
                           SHIFT_ENABLE1, ZeroPad => ZeroPad);
   U_1 : SHIFT_REG_16_3 port map( CLK => n2, RST_N => RST, SHIFT_ENABLE => 
                           SHIFT_ENABLE, D_ORIG => D_ORIG, RCV_DATA(15) => 
                           RCV_DATA_15_port, RCV_DATA(14) => RCV_DATA_14_port, 
                           RCV_DATA(13) => RCV_DATA_13_port, RCV_DATA(12) => 
                           RCV_DATA_12_port, RCV_DATA(11) => RCV_DATA_11_port, 
                           RCV_DATA(10) => RCV_DATA_10_port, RCV_DATA(9) => 
                           RCV_DATA_9_port, RCV_DATA(8) => RCV_DATA_8_port, 
                           RCV_DATA(7) => RCV_DATA_7_port, RCV_DATA(6) => 
                           RCV_DATA_6_port, RCV_DATA(5) => RCV_DATA_5_port, 
                           RCV_DATA(4) => RCV_DATA_4_port, RCV_DATA(3) => 
                           RCV_DATA_3_port, RCV_DATA(2) => RCV_DATA_2_port, 
                           RCV_DATA(1) => RCV_DATA_1_port, RCV_DATA(0) => 
                           RCV_DATA_0_port);
   U_2 : SHIFT_REG_16_2 port map( CLK => n2, RST_N => RST, SHIFT_ENABLE => 
                           SHIFT_ENABLE1, D_ORIG => D_ORIG, RCV_DATA(15) => 
                           RCV_DATA1_15_port, RCV_DATA(14) => RCV_DATA1_14_port
                           , RCV_DATA(13) => RCV_DATA1_13_port, RCV_DATA(12) =>
                           RCV_DATA1_12_port, RCV_DATA(11) => RCV_DATA1_11_port
                           , RCV_DATA(10) => RCV_DATA1_10_port, RCV_DATA(9) => 
                           RCV_DATA1_9_port, RCV_DATA(8) => RCV_DATA1_8_port, 
                           RCV_DATA(7) => RCV_DATA1_7_port, RCV_DATA(6) => 
                           RCV_DATA1_6_port, RCV_DATA(5) => RCV_DATA1_5_port, 
                           RCV_DATA(4) => RCV_DATA1_4_port, RCV_DATA(3) => 
                           RCV_DATA1_3_port, RCV_DATA(2) => RCV_DATA1_2_port, 
                           RCV_DATA(1) => RCV_DATA1_1_port, RCV_DATA(0) => 
                           RCV_DATA1_0_port);
   U1 : INVX2 port map( A => n3, Y => n2);
   U2 : INVX2 port map( A => BCLK, Y => n3);
   U3 : INVX2 port map( A => SHIFT_ENABLE, Y => n1);
   U4 : INVX2 port map( A => n34, Y => DATA(0));
   U5 : INVX2 port map( A => n27, Y => DATA(1));
   U6 : INVX2 port map( A => n26, Y => DATA(2));
   U7 : INVX2 port map( A => n25, Y => DATA(3));
   U8 : INVX2 port map( A => n24, Y => DATA(4));
   U9 : INVX2 port map( A => n23, Y => DATA(5));
   U10 : INVX2 port map( A => n22, Y => DATA(6));
   U11 : INVX2 port map( A => n21, Y => DATA(7));
   U12 : INVX2 port map( A => n20, Y => DATA(8));
   U13 : INVX2 port map( A => n19, Y => DATA(9));
   U14 : INVX2 port map( A => n33, Y => DATA(10));
   U15 : INVX2 port map( A => n32, Y => DATA(11));
   U16 : INVX2 port map( A => n31, Y => DATA(12));
   U17 : INVX2 port map( A => n30, Y => DATA(13));
   U18 : INVX2 port map( A => n29, Y => DATA(14));
   U36 : INVX2 port map( A => n28, Y => DATA(15));
   U37 : INVX2 port map( A => SDI, Y => n36);

end SYN_struct;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity FRAME_SYNC is

   port( CLK, RST, EN : in std_logic;  SYNC : out std_logic);

end FRAME_SYNC;

architecture SYN_tag_arch of FRAME_SYNC is

   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component MUX2X1
      port( B, A, S : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component NOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component AND2X2
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component FRAME_SYNC_DW01_inc_0
      port( A : in std_logic_vector (6 downto 0);  SUM : out std_logic_vector 
            (6 downto 0));
   end component;
   
   component XNOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND3X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI21X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component AOI21X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component AOI22X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component OR2X2
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component DFFSR
      port( D, CLK, R, S : in std_logic;  Q : out std_logic);
   end component;
   
   signal state_2_port, state_1_port, state_0_port, bitcount_2_port, 
      bitcount_1_port, bitcount_0_port, bytecount_6_port, bytecount_5_port, 
      bytecount_4_port, bytecount_3_port, bytecount_2_port, bytecount_1_port, 
      bytecount_0_port, nextstate_2_port, nextstate_1_port, nextstate_0_port, 
      nextbitcount_2_port, nextbitcount_1_port, nextbitcount_0_port, 
      nextbytecount_6_port, nextbytecount_5_port, nextbytecount_4_port, 
      nextbytecount_3_port, nextbytecount_2_port, nextbytecount_1_port, 
      nextbytecount_0_port, sync_int, N51, N52, N53, N54, N55, N56, N57, N91, 
      N92, N93, N94, N95, N157, N158, N159, N217, N218, N219, N220, N221, N222,
      N223, N230, N231, N232, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, 
      n18, n19, n20, n21, n41, n42, n43, n44, n45, n46, n47, n49, n50, n51_port
      , n52_port, n53_port, n54_port, n55_port, n56_port, n57_port, n58, n59, 
      n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74
      , n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, 
      n89, n90, n91_port, n92_port, n1, n2, n3, n4, n5, n6, n7, n22, n23, n24, 
      n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39
      , n40, n48, n93_port, n94_port, n95_port, n96, n97, n98, n99, n100, n101,
      n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, 
      n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, 
      n126, n127, n128 : std_logic;

begin
   
   bitcount_reg_0_inst : DFFSR port map( D => n92_port, CLK => CLK, R => RST, S
                           => n21, Q => bitcount_0_port);
   state_reg_0_inst : DFFSR port map( D => n89, CLK => CLK, R => RST, S => n20,
                           Q => state_0_port);
   state_reg_1_inst : DFFSR port map( D => n90, CLK => CLK, R => RST, S => n19,
                           Q => state_1_port);
   state_reg_2_inst : DFFSR port map( D => n91_port, CLK => CLK, R => RST, S =>
                           n18, Q => state_2_port);
   bitcount_reg_2_inst : DFFSR port map( D => n88, CLK => CLK, R => RST, S => 
                           n17, Q => bitcount_2_port);
   bitcount_reg_1_inst : DFFSR port map( D => n87, CLK => CLK, R => RST, S => 
                           n16, Q => bitcount_1_port);
   sync_int_f_reg : DFFSR port map( D => sync_int, CLK => CLK, R => RST, S => 
                           n15, Q => SYNC);
   bytecount_reg_6_inst : DFFSR port map( D => n86, CLK => CLK, R => RST, S => 
                           n14, Q => bytecount_6_port);
   bytecount_reg_5_inst : DFFSR port map( D => n85, CLK => CLK, R => RST, S => 
                           n13, Q => bytecount_5_port);
   bytecount_reg_4_inst : DFFSR port map( D => n84, CLK => CLK, R => RST, S => 
                           n12, Q => bytecount_4_port);
   bytecount_reg_3_inst : DFFSR port map( D => n83, CLK => CLK, R => RST, S => 
                           n11, Q => bytecount_3_port);
   bytecount_reg_2_inst : DFFSR port map( D => n82, CLK => CLK, R => RST, S => 
                           n10, Q => bytecount_2_port);
   bytecount_reg_1_inst : DFFSR port map( D => n81, CLK => CLK, R => RST, S => 
                           n9, Q => bytecount_1_port);
   bytecount_reg_0_inst : DFFSR port map( D => n80, CLK => CLK, R => RST, S => 
                           n8, Q => bytecount_0_port);
   n8 <= '1';
   n9 <= '1';
   n10 <= '1';
   n11 <= '1';
   n12 <= '1';
   n13 <= '1';
   n14 <= '1';
   n15 <= '1';
   n16 <= '1';
   n17 <= '1';
   n18 <= '1';
   n19 <= '1';
   n20 <= '1';
   n21 <= '1';
   U18 : OR2X2 port map( A => N92, B => n114, Y => n42);
   U19 : AND2X2 port map( A => N57, B => n74, Y => N223);
   U20 : AND2X2 port map( A => N56, B => n74, Y => N222);
   U21 : AND2X2 port map( A => N55, B => n74, Y => N221);
   U22 : AND2X2 port map( A => N54, B => n74, Y => N220);
   U23 : AND2X2 port map( A => N53, B => n74, Y => N219);
   U24 : AND2X2 port map( A => N52, B => n74, Y => N218);
   U25 : AND2X2 port map( A => N51, B => n74, Y => N217);
   U45 : OAI21X1 port map( A => n41, B => n42, C => n43, Y => sync_int);
   U46 : AOI22X1 port map( A => state_0_port, B => n44, C => n45, D => n46, Y 
                           => n43);
   U47 : NOR2X1 port map( A => n47, B => n108, Y => n46);
   U48 : AOI22X1 port map( A => bitcount_1_port, B => n113, C => n118, D => 
                           n117, Y => n47);
   U49 : NOR2X1 port map( A => n114, B => n116, Y => n45);
   U50 : NAND2X1 port map( A => n108, B => n116, Y => n41);
   U51 : OAI21X1 port map( A => n1, B => n128, C => n49, Y => n80);
   U52 : NAND2X1 port map( A => nextbytecount_0_port, B => n1, Y => n49);
   U53 : OAI21X1 port map( A => n1, B => n127, C => n50, Y => n81);
   U54 : NAND2X1 port map( A => nextbytecount_1_port, B => n1, Y => n50);
   U55 : OAI21X1 port map( A => n1, B => n126, C => n51_port, Y => n82);
   U56 : NAND2X1 port map( A => nextbytecount_2_port, B => n1, Y => n51_port);
   U57 : OAI21X1 port map( A => n1, B => n125, C => n52_port, Y => n83);
   U58 : NAND2X1 port map( A => nextbytecount_3_port, B => n1, Y => n52_port);
   U59 : OAI21X1 port map( A => n1, B => n124, C => n53_port, Y => n84);
   U60 : NAND2X1 port map( A => nextbytecount_4_port, B => n1, Y => n53_port);
   U61 : OAI21X1 port map( A => n1, B => n123, C => n54_port, Y => n85);
   U62 : NAND2X1 port map( A => nextbytecount_5_port, B => n1, Y => n54_port);
   U63 : OAI21X1 port map( A => n1, B => n122, C => n55_port, Y => n86);
   U64 : NAND2X1 port map( A => nextbytecount_6_port, B => n1, Y => n55_port);
   U66 : OAI21X1 port map( A => n112, B => n118, C => n58, Y => n87);
   U67 : NAND2X1 port map( A => nextbitcount_1_port, B => n112, Y => n58);
   U68 : OAI21X1 port map( A => n112, B => n117, C => n59, Y => n88);
   U69 : NAND2X1 port map( A => nextbitcount_2_port, B => n112, Y => n59);
   U70 : OAI21X1 port map( A => n60, B => n108, C => n61, Y => n89);
   U71 : NAND2X1 port map( A => nextstate_0_port, B => n60, Y => n61);
   U72 : OAI21X1 port map( A => n60, B => n114, C => n62, Y => n90);
   U73 : NAND2X1 port map( A => nextstate_1_port, B => n60, Y => n62);
   U74 : OAI21X1 port map( A => n60, B => n116, C => n63, Y => n91_port);
   U75 : NAND2X1 port map( A => nextstate_2_port, B => n60, Y => n63);
   U76 : AOI21X1 port map( A => n44, B => n64, C => n57_port, Y => n60);
   U77 : OAI22X1 port map( A => n108, B => n65, C => n114, D => n65, Y => 
                           n57_port);
   U78 : OAI21X1 port map( A => n117, B => n66, C => n111, Y => n65);
   U79 : NOR2X1 port map( A => n111, B => state_0_port, Y => n64);
   U80 : OAI21X1 port map( A => n113, B => n112, C => n67, Y => n92_port);
   U81 : NAND2X1 port map( A => nextbitcount_0_port, B => n112, Y => n67);
   U82 : OAI21X1 port map( A => state_0_port, B => n115, C => n68, Y => 
                           n56_port);
   U83 : OAI21X1 port map( A => state_1_port, B => state_0_port, C => n110, Y 
                           => n68);
   U84 : NOR2X1 port map( A => state_1_port, B => state_2_port, Y => n44);
   U85 : NOR2X1 port map( A => n69, B => n70, Y => N95);
   U86 : OAI21X1 port map( A => n110, B => n120, C => n71, Y => N94);
   U87 : NOR2X1 port map( A => n69, B => n72, Y => N93);
   U88 : NOR2X1 port map( A => n73, B => bytecount_5_port, Y => n69);
   U89 : NOR2X1 port map( A => n121, B => n70, Y => N232);
   U90 : NOR2X1 port map( A => n121, B => n71, Y => N231);
   U91 : OAI21X1 port map( A => n110, B => n74, C => n72, Y => N230);
   U92 : NAND3X1 port map( A => n75, B => bytecount_5_port, C => n76, Y => n74)
                           ;
   U93 : NOR2X1 port map( A => n122, B => n77, Y => n76);
   U94 : NOR2X1 port map( A => n125, B => n124, Y => n75);
   U95 : NAND2X1 port map( A => n70, B => n78, Y => N159);
   U96 : NAND2X1 port map( A => n111, B => state_2_port, Y => n70);
   U97 : NAND2X1 port map( A => n71, B => n78, Y => N158);
   U98 : NAND2X1 port map( A => n111, B => state_1_port, Y => n71);
   U99 : NAND2X1 port map( A => n72, B => n78, Y => N157);
   U100 : NAND3X1 port map( A => bytecount_5_port, B => n111, C => n119, Y => 
                           n78);
   U101 : NAND3X1 port map( A => n124, B => n122, C => n79, Y => n73);
   U102 : NOR2X1 port map( A => bytecount_3_port, B => n77, Y => n79);
   U103 : NAND3X1 port map( A => n128, B => n127, C => bytecount_2_port, Y => 
                           n77);
   U104 : NAND2X1 port map( A => n111, B => state_0_port, Y => n72);
   U105 : XOR2X1 port map( A => n66, B => n117, Y => N92);
   U106 : NAND2X1 port map( A => bitcount_1_port, B => bitcount_0_port, Y => 
                           n66);
   U107 : XNOR2X1 port map( A => n118, B => bitcount_0_port, Y => N91);
   r87 : FRAME_SYNC_DW01_inc_0 port map( A(6) => bytecount_6_port, A(5) => 
                           bytecount_5_port, A(4) => bytecount_4_port, A(3) => 
                           bytecount_3_port, A(2) => bytecount_2_port, A(1) => 
                           bytecount_1_port, A(0) => bytecount_0_port, SUM(6) 
                           => N57, SUM(5) => N56, SUM(4) => N55, SUM(3) => N54,
                           SUM(2) => N53, SUM(1) => N52, SUM(0) => N51);
   U4 : NOR2X1 port map( A => n56_port, B => n57_port, Y => n1);
   U26 : AND2X2 port map( A => n109, B => n114, Y => n2);
   U27 : INVX2 port map( A => n116, Y => n109);
   U28 : INVX2 port map( A => n110, Y => n111);
   U29 : INVX2 port map( A => EN, Y => n110);
   U30 : INVX2 port map( A => n108, Y => n107);
   U31 : INVX2 port map( A => state_0_port, Y => n108);
   U32 : XOR2X1 port map( A => n107, B => n109, Y => n3);
   U33 : MUX2X1 port map( B => n5, A => n6, S => n107, Y => n4);
   U34 : MUX2X1 port map( B => n7, A => n103, S => state_1_port, Y => 
                           nextbitcount_0_port);
   U35 : MUX2X1 port map( B => n23, A => n24, S => n107, Y => n22);
   U36 : MUX2X1 port map( B => n25, A => n101, S => state_1_port, Y => 
                           nextbitcount_1_port);
   U37 : MUX2X1 port map( B => n27, A => n28, S => n107, Y => n26);
   U38 : MUX2X1 port map( B => n29, A => n102, S => state_1_port, Y => 
                           nextbitcount_2_port);
   U39 : MUX2X1 port map( B => n30, A => n31, S => state_1_port, Y => 
                           nextstate_2_port);
   U40 : MUX2X1 port map( B => n33, A => n34, S => state_2_port, Y => n32);
   U41 : NOR2X1 port map( A => n108, B => n110, Y => n35);
   U42 : MUX2X1 port map( B => n36, A => n105, S => state_1_port, Y => 
                           nextstate_1_port);
   U43 : MUX2X1 port map( B => n38, A => n39, S => state_2_port, Y => n37);
   U44 : NAND2X1 port map( A => n107, B => n110, Y => n40);
   U65 : MUX2X1 port map( B => n48, A => n106, S => state_1_port, Y => 
                           nextstate_0_port);
   U108 : MUX2X1 port map( B => N51, A => N217, S => n2, Y => n93_port);
   U109 : MUX2X1 port map( B => N52, A => N218, S => n2, Y => n94_port);
   U110 : MUX2X1 port map( B => N53, A => N219, S => n2, Y => n95_port);
   U111 : MUX2X1 port map( B => N54, A => N220, S => n2, Y => n96);
   U112 : MUX2X1 port map( B => N55, A => N221, S => n2, Y => n97);
   U113 : MUX2X1 port map( B => N56, A => N222, S => n2, Y => n98);
   U114 : MUX2X1 port map( B => N57, A => N223, S => n2, Y => n99);
   U115 : MUX2X1 port map( B => n113, A => n113, S => state_2_port, Y => n6);
   U116 : MUX2X1 port map( B => n113, A => n113, S => state_2_port, Y => n5);
   U117 : MUX2X1 port map( B => n113, A => n113, S => state_2_port, Y => n7);
   U118 : MUX2X1 port map( B => N91, A => N91, S => state_2_port, Y => n24);
   U119 : MUX2X1 port map( B => N91, A => N91, S => state_2_port, Y => n23);
   U120 : MUX2X1 port map( B => N91, A => N91, S => n109, Y => n25);
   U121 : MUX2X1 port map( B => N92, A => N92, S => n109, Y => n28);
   U122 : MUX2X1 port map( B => N92, A => N92, S => n109, Y => n27);
   U123 : MUX2X1 port map( B => N92, A => N92, S => n109, Y => n29);
   U124 : MUX2X1 port map( B => N95, A => N159, S => n109, Y => n100);
   U125 : MUX2X1 port map( B => n111, A => n104, S => n3, Y => n31);
   U126 : NAND2X1 port map( A => N232, B => state_2_port, Y => n30);
   U127 : MUX2X1 port map( B => n111, A => N94, S => n107, Y => n33);
   U128 : NAND2X1 port map( A => N158, B => n108, Y => n34);
   U129 : MUX2X1 port map( B => n35, A => N231, S => n109, Y => n36);
   U130 : MUX2X1 port map( B => N157, A => n111, S => n107, Y => n39);
   U131 : NAND2X1 port map( A => N93, B => n107, Y => n38);
   U132 : MUX2X1 port map( B => n40, A => N230, S => n109, Y => n48);
   U133 : INVX2 port map( A => n99, Y => nextbytecount_6_port);
   U134 : INVX2 port map( A => n98, Y => nextbytecount_5_port);
   U135 : INVX2 port map( A => n97, Y => nextbytecount_4_port);
   U136 : INVX2 port map( A => n96, Y => nextbytecount_3_port);
   U137 : INVX2 port map( A => n95_port, Y => nextbytecount_2_port);
   U138 : INVX2 port map( A => n94_port, Y => nextbytecount_1_port);
   U139 : INVX2 port map( A => n93_port, Y => nextbytecount_0_port);
   U140 : INVX2 port map( A => n22, Y => n101);
   U141 : INVX2 port map( A => n26, Y => n102);
   U142 : INVX2 port map( A => n4, Y => n103);
   U143 : INVX2 port map( A => n100, Y => n104);
   U144 : INVX2 port map( A => n32, Y => n105);
   U145 : INVX2 port map( A => n37, Y => n106);
   U146 : INVX2 port map( A => n56_port, Y => n112);
   U147 : INVX2 port map( A => bitcount_0_port, Y => n113);
   U148 : INVX2 port map( A => state_1_port, Y => n114);
   U149 : INVX2 port map( A => n44, Y => n115);
   U150 : INVX2 port map( A => state_2_port, Y => n116);
   U151 : INVX2 port map( A => bitcount_2_port, Y => n117);
   U152 : INVX2 port map( A => bitcount_1_port, Y => n118);
   U153 : INVX2 port map( A => n73, Y => n119);
   U154 : INVX2 port map( A => n69, Y => n120);
   U155 : INVX2 port map( A => n74, Y => n121);
   U156 : INVX2 port map( A => bytecount_6_port, Y => n122);
   U157 : INVX2 port map( A => bytecount_5_port, Y => n123);
   U158 : INVX2 port map( A => bytecount_4_port, Y => n124);
   U159 : INVX2 port map( A => bytecount_3_port, Y => n125);
   U160 : INVX2 port map( A => bytecount_2_port, Y => n126);
   U161 : INVX2 port map( A => bytecount_1_port, Y => n127);
   U162 : INVX2 port map( A => bytecount_0_port, Y => n128);

end SYN_tag_arch;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity CLK_DIV is

   port( RST, CLK_in : in std_logic;  CLK_48, CLK_24 : out std_logic);

end CLK_DIV;

architecture SYN_DIV_arch of CLK_DIV is

   component INVX2
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component DFFSR
      port( D, CLK, R, S : in std_logic;  Q : out std_logic);
   end component;
   
   signal CLK_48_port, CLK_24_port, count_0_port, n1, n2, n3, n7, n4, n5 : 
      std_logic;

begin
   CLK_48 <= CLK_48_port;
   CLK_24 <= CLK_24_port;
   
   count_reg_0_inst : DFFSR port map( D => n5, CLK => CLK_in, R => RST, S => n3
                           , Q => count_0_port);
   output24_reg : DFFSR port map( D => n7, CLK => CLK_in, R => n2, S => RST, Q 
                           => CLK_24_port);
   output48_reg : DFFSR port map( D => n4, CLK => CLK_in, R => RST, S => n1, Q 
                           => CLK_48_port);
   n1 <= '1';
   n2 <= '1';
   n3 <= '1';
   U9 : XOR2X1 port map( A => CLK_24_port, B => n5, Y => n7);
   U5 : INVX2 port map( A => CLK_48_port, Y => n4);
   U7 : INVX2 port map( A => count_0_port, Y => n5);

end SYN_DIV_arch;

library IEEE,OSU_AMI05;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_AZALIA_BLOCK.all;

entity AZALIA_BLOCK is

   port( CLK : in std_logic;  DATA_in : in std_logic_vector (7 downto 0);  RST,
         Rx_DATA_STB, SDI0, SDI1, Tx_DATA_STB : in std_logic;  ERR, CRIT, 
         NEW_Rx_DATA, REQ_Tx_DATA : out std_logic;  ADDR : out std_logic_vector
         (11 downto 0);  BUSY : out std_logic;  DATA_out : out std_logic_vector
         (7 downto 0);  OWN_MEM, RE, RW, SDO, WE, SYNC : out std_logic);

end AZALIA_BLOCK;

architecture SYN_struct of AZALIA_BLOCK is

   component OUTPUT_BLOCK
      port( CLK, RST, EN, SYNC, STB : in std_logic;  DATA : in std_logic_vector
            (15 downto 0);  REQ, SDO : out std_logic);
   end component;
   
   component MEMORY_CONTROLLER
      port( CLK, RST : in std_logic;  EN, ERR, CRIT, REQ_Tx_DATA : out 
            std_logic;  Tx_DATA_STB : in std_logic;  NEW_Rx_DATA : out 
            std_logic;  Rx_DATA_STB : in std_logic;  ADDR : out 
            std_logic_vector (11 downto 0);  DATA_in : in std_logic_vector (7 
            downto 0);  DATA_out : out std_logic_vector (7 downto 0);  RW, RE, 
            WE, BUSY, OWN_MEM : out std_logic;  OUTDATA : out std_logic_vector 
            (15 downto 0);  OUTSTRB : out std_logic;  OUTREQ : in std_logic;  
            I0DATA : in std_logic_vector (15 downto 0);  I0DRW, I0DRB : in 
            std_logic;  I0STRB : out std_logic;  I1DATA : in std_logic_vector 
            (15 downto 0);  I1DRW, I1DRB : in std_logic;  I1STRB : out 
            std_logic;  SYNC : in std_logic);
   end component;
   
   component IN_BLOCK_0
      port( BCLK, EN, RST, SDI, STRB, SYNC : in std_logic;  DATA : out 
            std_logic_vector (15 downto 0);  DataReadyB, DataReadyW : out 
            std_logic);
   end component;
   
   component IN_BLOCK_1
      port( BCLK, EN, RST, SDI, STRB, SYNC : in std_logic;  DATA : out 
            std_logic_vector (15 downto 0);  DataReadyB, DataReadyW : out 
            std_logic);
   end component;
   
   component FRAME_SYNC
      port( CLK, RST, EN : in std_logic;  SYNC : out std_logic);
   end component;
   
   component CLK_DIV
      port( RST, CLK_in : in std_logic;  CLK_48, CLK_24 : out std_logic);
   end component;
   
   signal SYNC_port, CLK_24, CLK_48, EN, I0STRB, I0DATA_15_port, I0DATA_14_port
      , I0DATA_13_port, I0DATA_12_port, I0DATA_11_port, I0DATA_10_port, 
      I0DATA_9_port, I0DATA_8_port, I0DATA_7_port, I0DATA_6_port, I0DATA_5_port
      , I0DATA_4_port, I0DATA_3_port, I0DATA_2_port, I0DATA_1_port, 
      I0DATA_0_port, I0DRB, I0DRW, I1STRB, I1DATA_15_port, I1DATA_14_port, 
      I1DATA_13_port, I1DATA_12_port, I1DATA_11_port, I1DATA_10_port, 
      I1DATA_9_port, I1DATA_8_port, I1DATA_7_port, I1DATA_6_port, I1DATA_5_port
      , I1DATA_4_port, I1DATA_3_port, I1DATA_2_port, I1DATA_1_port, 
      I1DATA_0_port, I1DRB, DataReadyW, REQ, OUTDATA_15_port, OUTDATA_14_port, 
      OUTDATA_13_port, OUTDATA_12_port, OUTDATA_11_port, OUTDATA_10_port, 
      OUTDATA_9_port, OUTDATA_8_port, OUTDATA_7_port, OUTDATA_6_port, 
      OUTDATA_5_port, OUTDATA_4_port, OUTDATA_3_port, OUTDATA_2_port, 
      OUTDATA_1_port, OUTDATA_0_port, OUTSTRB : std_logic;

begin
   SYNC <= SYNC_port;
   
   CLK_DIV_BLK : CLK_DIV port map( RST => RST, CLK_in => CLK, CLK_48 => CLK_48,
                           CLK_24 => CLK_24);
   SYNC_BLK : FRAME_SYNC port map( CLK => CLK_48, RST => RST, EN => EN, SYNC =>
                           SYNC_port);
   IN0_BLK : IN_BLOCK_1 port map( BCLK => CLK_24, EN => EN, RST => RST, SDI => 
                           SDI0, STRB => I0STRB, SYNC => SYNC_port, DATA(15) =>
                           I0DATA_15_port, DATA(14) => I0DATA_14_port, DATA(13)
                           => I0DATA_13_port, DATA(12) => I0DATA_12_port, 
                           DATA(11) => I0DATA_11_port, DATA(10) => 
                           I0DATA_10_port, DATA(9) => I0DATA_9_port, DATA(8) =>
                           I0DATA_8_port, DATA(7) => I0DATA_7_port, DATA(6) => 
                           I0DATA_6_port, DATA(5) => I0DATA_5_port, DATA(4) => 
                           I0DATA_4_port, DATA(3) => I0DATA_3_port, DATA(2) => 
                           I0DATA_2_port, DATA(1) => I0DATA_1_port, DATA(0) => 
                           I0DATA_0_port, DataReadyB => I0DRB, DataReadyW => 
                           I0DRW);
   IN1_BLK : IN_BLOCK_0 port map( BCLK => CLK_24, EN => EN, RST => RST, SDI => 
                           SDI1, STRB => I1STRB, SYNC => SYNC_port, DATA(15) =>
                           I1DATA_15_port, DATA(14) => I1DATA_14_port, DATA(13)
                           => I1DATA_13_port, DATA(12) => I1DATA_12_port, 
                           DATA(11) => I1DATA_11_port, DATA(10) => 
                           I1DATA_10_port, DATA(9) => I1DATA_9_port, DATA(8) =>
                           I1DATA_8_port, DATA(7) => I1DATA_7_port, DATA(6) => 
                           I1DATA_6_port, DATA(5) => I1DATA_5_port, DATA(4) => 
                           I1DATA_4_port, DATA(3) => I1DATA_3_port, DATA(2) => 
                           I1DATA_2_port, DATA(1) => I1DATA_1_port, DATA(0) => 
                           I1DATA_0_port, DataReadyB => I1DRB, DataReadyW => 
                           DataReadyW);
   MEM_CTL_BLK : MEMORY_CONTROLLER port map( CLK => CLK, RST => RST, EN => EN, 
                           ERR => ERR, CRIT => CRIT, REQ_Tx_DATA => REQ_Tx_DATA
                           , Tx_DATA_STB => Tx_DATA_STB, NEW_Rx_DATA => 
                           NEW_Rx_DATA, Rx_DATA_STB => Rx_DATA_STB, ADDR(11) =>
                           ADDR(11), ADDR(10) => ADDR(10), ADDR(9) => ADDR(9), 
                           ADDR(8) => ADDR(8), ADDR(7) => ADDR(7), ADDR(6) => 
                           ADDR(6), ADDR(5) => ADDR(5), ADDR(4) => ADDR(4), 
                           ADDR(3) => ADDR(3), ADDR(2) => ADDR(2), ADDR(1) => 
                           ADDR(1), ADDR(0) => ADDR(0), DATA_in(7) => 
                           DATA_in(7), DATA_in(6) => DATA_in(6), DATA_in(5) => 
                           DATA_in(5), DATA_in(4) => DATA_in(4), DATA_in(3) => 
                           DATA_in(3), DATA_in(2) => DATA_in(2), DATA_in(1) => 
                           DATA_in(1), DATA_in(0) => DATA_in(0), DATA_out(7) =>
                           DATA_out(7), DATA_out(6) => DATA_out(6), DATA_out(5)
                           => DATA_out(5), DATA_out(4) => DATA_out(4), 
                           DATA_out(3) => DATA_out(3), DATA_out(2) => 
                           DATA_out(2), DATA_out(1) => DATA_out(1), DATA_out(0)
                           => DATA_out(0), RW => RW, RE => RE, WE => WE, BUSY 
                           => BUSY, OWN_MEM => OWN_MEM, OUTDATA(15) => 
                           OUTDATA_15_port, OUTDATA(14) => OUTDATA_14_port, 
                           OUTDATA(13) => OUTDATA_13_port, OUTDATA(12) => 
                           OUTDATA_12_port, OUTDATA(11) => OUTDATA_11_port, 
                           OUTDATA(10) => OUTDATA_10_port, OUTDATA(9) => 
                           OUTDATA_9_port, OUTDATA(8) => OUTDATA_8_port, 
                           OUTDATA(7) => OUTDATA_7_port, OUTDATA(6) => 
                           OUTDATA_6_port, OUTDATA(5) => OUTDATA_5_port, 
                           OUTDATA(4) => OUTDATA_4_port, OUTDATA(3) => 
                           OUTDATA_3_port, OUTDATA(2) => OUTDATA_2_port, 
                           OUTDATA(1) => OUTDATA_1_port, OUTDATA(0) => 
                           OUTDATA_0_port, OUTSTRB => OUTSTRB, OUTREQ => REQ, 
                           I0DATA(15) => I0DATA_15_port, I0DATA(14) => 
                           I0DATA_14_port, I0DATA(13) => I0DATA_13_port, 
                           I0DATA(12) => I0DATA_12_port, I0DATA(11) => 
                           I0DATA_11_port, I0DATA(10) => I0DATA_10_port, 
                           I0DATA(9) => I0DATA_9_port, I0DATA(8) => 
                           I0DATA_8_port, I0DATA(7) => I0DATA_7_port, I0DATA(6)
                           => I0DATA_6_port, I0DATA(5) => I0DATA_5_port, 
                           I0DATA(4) => I0DATA_4_port, I0DATA(3) => 
                           I0DATA_3_port, I0DATA(2) => I0DATA_2_port, I0DATA(1)
                           => I0DATA_1_port, I0DATA(0) => I0DATA_0_port, I0DRW 
                           => I0DRW, I0DRB => I0DRB, I0STRB => I0STRB, 
                           I1DATA(15) => I1DATA_15_port, I1DATA(14) => 
                           I1DATA_14_port, I1DATA(13) => I1DATA_13_port, 
                           I1DATA(12) => I1DATA_12_port, I1DATA(11) => 
                           I1DATA_11_port, I1DATA(10) => I1DATA_10_port, 
                           I1DATA(9) => I1DATA_9_port, I1DATA(8) => 
                           I1DATA_8_port, I1DATA(7) => I1DATA_7_port, I1DATA(6)
                           => I1DATA_6_port, I1DATA(5) => I1DATA_5_port, 
                           I1DATA(4) => I1DATA_4_port, I1DATA(3) => 
                           I1DATA_3_port, I1DATA(2) => I1DATA_2_port, I1DATA(1)
                           => I1DATA_1_port, I1DATA(0) => I1DATA_0_port, I1DRW 
                           => DataReadyW, I1DRB => I1DRB, I1STRB => I1STRB, 
                           SYNC => SYNC_port);
   OUT_BLK : OUTPUT_BLOCK port map( CLK => CLK_48, RST => RST, EN => EN, SYNC 
                           => SYNC_port, STB => OUTSTRB, DATA(15) => 
                           OUTDATA_15_port, DATA(14) => OUTDATA_14_port, 
                           DATA(13) => OUTDATA_13_port, DATA(12) => 
                           OUTDATA_12_port, DATA(11) => OUTDATA_11_port, 
                           DATA(10) => OUTDATA_10_port, DATA(9) => 
                           OUTDATA_9_port, DATA(8) => OUTDATA_8_port, DATA(7) 
                           => OUTDATA_7_port, DATA(6) => OUTDATA_6_port, 
                           DATA(5) => OUTDATA_5_port, DATA(4) => OUTDATA_4_port
                           , DATA(3) => OUTDATA_3_port, DATA(2) => 
                           OUTDATA_2_port, DATA(1) => OUTDATA_1_port, DATA(0) 
                           => OUTDATA_0_port, REQ => REQ, SDO => SDO);

end SYN_struct;
